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Stefan Roesed07117e2007-02-20 10:27:08 +01001/*
Stefan Roese77c1f1d2009-11-19 14:03:17 +01002 * (C) Copyright 2007-2009
Stefan Roesed07117e2007-02-20 10:27:08 +01003 * Stefan Roese, DENX Software Engineering, sr@denx.de.
4 *
Wolfgang Denkd79de1d2013-07-08 09:37:19 +02005 * SPDX-License-Identifier: GPL-2.0+
Stefan Roesed07117e2007-02-20 10:27:08 +01006 */
7
8#ifndef _4xx_i2c_h_
9#define _4xx_i2c_h_
10
11#define IIC_OK 0
12#define IIC_NOK 1
13#define IIC_NOK_LA 2 /* Lost arbitration */
14#define IIC_NOK_ICT 3 /* Incomplete transfer */
15#define IIC_NOK_XFRA 4 /* Transfer aborted */
16#define IIC_NOK_DATA 5 /* No data in buffer */
17#define IIC_NOK_TOUT 6 /* Transfer timeout */
18
19#define IIC_TIMEOUT 1 /* 1 second */
20
21#if defined(CONFIG_I2C_MULTI_BUS)
22#define I2C_BUS_OFFS (i2c_bus_num * 0x100)
23#else
24#define I2C_BUS_OFFS (0x000)
25#endif /* CONFIG_I2C_MULTI_BUS */
26
27#if defined(CONFIG_440EP) || defined(CONFIG_440GR) || \
Stefan Roese50c05332008-03-11 15:07:10 +010028 defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
29 defined(CONFIG_460EX) || defined(CONFIG_460GT)
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020030#define I2C_BASE_ADDR (CONFIG_SYS_PERIPHERAL_BASE + 0x00000700 + I2C_BUS_OFFS)
Stefan Roese153b3e22007-10-05 17:10:59 +020031#elif defined(CONFIG_440) || defined(CONFIG_405EX)
Stefan Roesed07117e2007-02-20 10:27:08 +010032/* all remaining 440 variants */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020033#define I2C_BASE_ADDR (CONFIG_SYS_PERIPHERAL_BASE + 0x00000400 + I2C_BUS_OFFS)
Stefan Roesed07117e2007-02-20 10:27:08 +010034#else
35/* all 405 variants */
36#define I2C_BASE_ADDR (0xEF600500 + I2C_BUS_OFFS)
37#endif
38
Stefan Roese77c1f1d2009-11-19 14:03:17 +010039struct ppc4xx_i2c {
40 u8 mdbuf;
41 u8 res1;
42 u8 sdbuf;
43 u8 res2;
44 u8 lmadr;
45 u8 hmadr;
46 u8 cntl;
47 u8 mdcntl;
48 u8 sts;
49 u8 extsts;
50 u8 lsadr;
51 u8 hsadr;
52 u8 clkdiv;
53 u8 intrmsk;
54 u8 xfrcnt;
55 u8 xtcntlss;
56 u8 directcntl;
57 u8 intr;
58};
Stefan Roesed07117e2007-02-20 10:27:08 +010059
60/* MDCNTL Register Bit definition */
61#define IIC_MDCNTL_HSCL 0x01
62#define IIC_MDCNTL_EUBS 0x02
63#define IIC_MDCNTL_EINT 0x04
64#define IIC_MDCNTL_ESM 0x08
65#define IIC_MDCNTL_FSM 0x10
66#define IIC_MDCNTL_EGC 0x20
67#define IIC_MDCNTL_FMDB 0x40
68#define IIC_MDCNTL_FSDB 0x80
69
70/* CNTL Register Bit definition */
71#define IIC_CNTL_PT 0x01
72#define IIC_CNTL_READ 0x02
73#define IIC_CNTL_CHT 0x04
74#define IIC_CNTL_RPST 0x08
75/* bit 2/3 for Transfer count*/
76#define IIC_CNTL_AMD 0x40
77#define IIC_CNTL_HMT 0x80
78
79/* STS Register Bit definition */
80#define IIC_STS_PT 0x01
81#define IIC_STS_IRQA 0x02
82#define IIC_STS_ERR 0x04
83#define IIC_STS_SCMP 0x08
84#define IIC_STS_MDBF 0x10
85#define IIC_STS_MDBS 0x20
86#define IIC_STS_SLPR 0x40
87#define IIC_STS_SSS 0x80
88
89/* EXTSTS Register Bit definition */
90#define IIC_EXTSTS_XFRA 0x01
91#define IIC_EXTSTS_ICT 0x02
92#define IIC_EXTSTS_LA 0x04
93
94/* XTCNTLSS Register Bit definition */
95#define IIC_XTCNTLSS_SRST 0x01
96#define IIC_XTCNTLSS_EPI 0x02
97#define IIC_XTCNTLSS_SDBF 0x04
98#define IIC_XTCNTLSS_SBDD 0x08
99#define IIC_XTCNTLSS_SWS 0x10
100#define IIC_XTCNTLSS_SWC 0x20
101#define IIC_XTCNTLSS_SRS 0x40
102#define IIC_XTCNTLSS_SRC 0x80
103
104/* IICx_DIRECTCNTL register */
105#define IIC_DIRCNTL_SDAC 0x08
106#define IIC_DIRCNTL_SCC 0x04
107#define IIC_DIRCNTL_MSDA 0x02
108#define IIC_DIRCNTL_MSC 0x01
109
110#define DIRCTNL_FREE(v) (((v) & 0x0f) == 0x0f)
111#endif