| Michal Simek | 6101515 | 2016-05-26 08:06:38 +0200 | [diff] [blame] | 1 | CONFIG_ARM=y |
| Michal Simek | 6101515 | 2016-05-26 08:06:38 +0200 | [diff] [blame] | 2 | CONFIG_ARCH_ZYNQMP=y |
| Michal Simek | cbd9118 | 2016-06-03 11:35:17 +0200 | [diff] [blame] | 3 | CONFIG_SYS_MALLOC_F_LEN=0x8000 |
| Siva Durga Prasad Paladugu | 809438d | 2016-07-29 15:31:47 +0530 | [diff] [blame] | 4 | CONFIG_IDENT_STRING=" Xilinx ZynqMP ZC1751 xm018 dc4" |
| Michal Simek | 6101515 | 2016-05-26 08:06:38 +0200 | [diff] [blame] | 5 | CONFIG_SYS_TEXT_BASE=0x8000000 |
| 6 | CONFIG_DEFAULT_DEVICE_TREE="zynqmp-zc1751-xm018-dc4" |
| 7 | CONFIG_FIT=y |
| 8 | CONFIG_FIT_VERBOSE=y |
| Michal Simek | 437c59c | 2016-05-17 08:38:53 +0200 | [diff] [blame] | 9 | CONFIG_SPL_LOAD_FIT=y |
| Lokesh Vutla | fbad370 | 2016-10-08 14:41:44 -0400 | [diff] [blame] | 10 | # CONFIG_DISPLAY_CPUINFO is not set |
| Lokesh Vutla | 94d95e4 | 2016-10-11 21:33:46 -0400 | [diff] [blame] | 11 | # CONFIG_DISPLAY_BOARDINFO is not set |
| Simon Glass | ffe1976 | 2016-09-12 23:18:22 -0600 | [diff] [blame] | 12 | CONFIG_SPL=y |
| 13 | CONFIG_SPL_SYS_MALLOC_SIMPLE=y |
| Heiko Schocher | 1d12ba2 | 2016-10-06 07:55:15 +0200 | [diff] [blame] | 14 | CONFIG_SPL_OS_BOOT=y |
| Michal Simek | 6101515 | 2016-05-26 08:06:38 +0200 | [diff] [blame] | 15 | CONFIG_HUSH_PARSER=y |
| 16 | CONFIG_SYS_PROMPT="ZynqMP> " |
| 17 | # CONFIG_CMD_IMLS is not set |
| 18 | CONFIG_CMD_MEMTEST=y |
| 19 | # CONFIG_CMD_FLASH is not set |
| 20 | CONFIG_CMD_MMC=y |
| 21 | CONFIG_CMD_I2C=y |
| 22 | CONFIG_CMD_TFTPPUT=y |
| 23 | CONFIG_CMD_DHCP=y |
| 24 | CONFIG_CMD_MII=y |
| 25 | CONFIG_CMD_PING=y |
| 26 | CONFIG_CMD_TIME=y |
| 27 | CONFIG_CMD_TIMER=y |
| 28 | CONFIG_CMD_EXT2=y |
| 29 | CONFIG_CMD_EXT4=y |
| 30 | CONFIG_CMD_EXT4_WRITE=y |
| 31 | CONFIG_CMD_FAT=y |
| 32 | CONFIG_CMD_FS_GENERIC=y |
| Michal Simek | 4c1f7f8 | 2016-07-15 08:41:46 +0200 | [diff] [blame] | 33 | CONFIG_SPL_OF_CONTROL=y |
| Michal Simek | 6101515 | 2016-05-26 08:06:38 +0200 | [diff] [blame] | 34 | CONFIG_OF_EMBED=y |
| 35 | CONFIG_NET_RANDOM_ETHADDR=y |
| Michal Simek | b9c5d13 | 2016-07-27 15:08:03 +0200 | [diff] [blame] | 36 | CONFIG_SPL_DM=y |
| Michal Simek | 4c1f7f8 | 2016-07-15 08:41:46 +0200 | [diff] [blame] | 37 | CONFIG_SPL_DM_SEQ_ALIAS=y |
| Michal Simek | 1fa5255 | 2016-08-01 08:49:12 +0200 | [diff] [blame] | 38 | CONFIG_BLK=y |
| Siva Durga Prasad Paladugu | 460fdce | 2016-01-13 16:25:37 +0530 | [diff] [blame] | 39 | CONFIG_FPGA_XILINX=y |
| 40 | CONFIG_FPGA_ZYNQMPPL=y |
| Tom Rini | afea41d | 2016-09-08 16:11:59 -0400 | [diff] [blame] | 41 | CONFIG_DM_GPIO=y |
| Michal Simek | b9c5d13 | 2016-07-27 15:08:03 +0200 | [diff] [blame] | 42 | CONFIG_DM_I2C=y |
| Michal Simek | 6101515 | 2016-05-26 08:06:38 +0200 | [diff] [blame] | 43 | CONFIG_SYS_I2C_CADENCE=y |
| 44 | CONFIG_DM_MMC=y |
| Michal Simek | 1fa5255 | 2016-08-01 08:49:12 +0200 | [diff] [blame] | 45 | CONFIG_DM_MMC_OPS=y |
| Michal Simek | 6101515 | 2016-05-26 08:06:38 +0200 | [diff] [blame] | 46 | CONFIG_ZYNQ_SDHCI=y |
| 47 | CONFIG_DM_ETH=y |
| 48 | CONFIG_ZYNQ_GEM=y |
| 49 | CONFIG_DEBUG_UART=y |
| 50 | CONFIG_DEBUG_UART_ZYNQ=y |
| 51 | CONFIG_DEBUG_UART_BASE=0xff000000 |
| 52 | CONFIG_DEBUG_UART_CLOCK=100000000 |
| 53 | CONFIG_DEBUG_UART_ANNOUNCE=y |