blob: 1ab05ec9fd4300c2dabf87ad8b1452fa26d59fe9 [file] [log] [blame]
Shengzhou Liuf13321d2014-03-05 15:04:48 +08001/*
2 * Copyright 2009-2013 Freescale Semiconductor, Inc.
3 *
4 * SPDX-License-Identifier: GPL-2.0+
5 */
6
7#include <common.h>
8#include <command.h>
9#include <i2c.h>
10#include <netdev.h>
11#include <linux/compiler.h>
12#include <asm/mmu.h>
13#include <asm/processor.h>
14#include <asm/immap_85xx.h>
15#include <asm/fsl_law.h>
16#include <asm/fsl_serdes.h>
Shengzhou Liuf13321d2014-03-05 15:04:48 +080017#include <asm/fsl_liodn.h>
18#include <fm_eth.h>
19#include "t208xrdb.h"
20#include "cpld.h"
Ying Zhang3861e822015-03-10 14:21:36 +080021#include "../common/vid.h"
Shengzhou Liuf13321d2014-03-05 15:04:48 +080022
23DECLARE_GLOBAL_DATA_PTR;
24
25int checkboard(void)
26{
27 struct cpu_type *cpu = gd->arch.cpu;
28 static const char *freq[3] = {"100.00MHZ", "125.00MHz", "156.25MHZ"};
29
30 printf("Board: %sRDB, ", cpu->name);
31 printf("Board rev: 0x%02x CPLD ver: 0x%02x, boot from ",
32 CPLD_READ(hw_ver), CPLD_READ(sw_ver));
33
34#ifdef CONFIG_SDCARD
35 puts("SD/MMC\n");
36#elif CONFIG_SPIFLASH
37 puts("SPI\n");
38#else
39 u8 reg;
40
41 reg = CPLD_READ(flash_csr);
42
43 if (reg & CPLD_BOOT_SEL) {
44 puts("NAND\n");
45 } else {
46 reg = ((reg & CPLD_LBMAP_MASK) >> CPLD_LBMAP_SHIFT);
Shengzhou Liu14139832014-04-18 16:43:41 +080047 printf("NOR vBank%d\n", reg);
Shengzhou Liuf13321d2014-03-05 15:04:48 +080048 }
49#endif
50
51 puts("SERDES Reference Clocks:\n");
52 printf("SD1_CLK1=%s, SD1_CLK2=%s\n", freq[2], freq[0]);
53 printf("SD2_CLK1=%s, SD2_CLK2=%s\n", freq[0], freq[0]);
54
55 return 0;
56}
57
58int board_early_init_r(void)
59{
60 const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
York Sun220c3462014-06-24 21:16:20 -070061 int flash_esel = find_tlb_idx((void *)flashbase, 1);
Shengzhou Liuf13321d2014-03-05 15:04:48 +080062 /*
63 * Remap Boot flash + PROMJET region to caching-inhibited
64 * so that flash can be erased properly.
65 */
66
67 /* Flush d-cache and invalidate i-cache of any FLASH data */
68 flush_dcache();
69 invalidate_icache();
York Sun220c3462014-06-24 21:16:20 -070070 if (flash_esel == -1) {
71 /* very unlikely unless something is messed up */
72 puts("Error: Could not find TLB for FLASH BASE\n");
73 flash_esel = 2; /* give our best effort to continue */
74 } else {
75 /* invalidate existing TLB entry for flash + promjet */
76 disable_tlb(flash_esel);
77 }
Shengzhou Liuf13321d2014-03-05 15:04:48 +080078
79 set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS,
80 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
81 0, flash_esel, BOOKE_PAGESZ_256M, 1);
82
Ying Zhang3861e822015-03-10 14:21:36 +080083 /*
84 * Adjust core voltage according to voltage ID
85 * This function changes I2C mux to channel 2.
86 */
87 if (adjust_vdd(0))
88 printf("Warning: Adjusting core voltage failed.\n");
Shengzhou Liuf13321d2014-03-05 15:04:48 +080089 return 0;
90}
91
92unsigned long get_board_sys_clk(void)
93{
94 return CONFIG_SYS_CLK_FREQ;
95}
96
97unsigned long get_board_ddr_clk(void)
98{
99 return CONFIG_DDR_CLK_FREQ;
100}
101
102int misc_init_r(void)
103{
Shengzhou Liud703f662015-04-22 10:59:50 +0800104 u8 reg;
105
106 /* Reset CS4315 PHY */
107 reg = CPLD_READ(reset_ctl);
108 reg |= CPLD_RSTCON_EDC_RST;
109 CPLD_WRITE(reset_ctl, reg);
110
Shengzhou Liuf13321d2014-03-05 15:04:48 +0800111 return 0;
112}
113
Simon Glass2aec3cc2014-10-23 18:58:47 -0600114int ft_board_setup(void *blob, bd_t *bd)
Shengzhou Liuf13321d2014-03-05 15:04:48 +0800115{
116 phys_addr_t base;
117 phys_size_t size;
118
119 ft_cpu_setup(blob, bd);
120
121 base = getenv_bootm_low();
122 size = getenv_bootm_size();
123
124 fdt_fixup_memory(blob, (u64)base, (u64)size);
125
126#ifdef CONFIG_PCI
127 pci_of_setup(blob, bd);
128#endif
129
130 fdt_fixup_liodn(blob);
Sriram Dash9fd465c2016-09-16 17:12:15 +0530131 fsl_fdt_fixup_dr_usb(blob, bd);
Shengzhou Liuf13321d2014-03-05 15:04:48 +0800132
133#ifdef CONFIG_SYS_DPAA_FMAN
134 fdt_fixup_fman_ethernet(blob);
135 fdt_fixup_board_enet(blob);
136#endif
Simon Glass2aec3cc2014-10-23 18:58:47 -0600137
138 return 0;
Shengzhou Liuf13321d2014-03-05 15:04:48 +0800139}