| Mingkai Hu | d239651 | 2016-09-07 18:47:28 +0800 | [diff] [blame] | 1 | /* |
| 2 | * Device Tree Include file for Freescale Layerscape-1046A family SoC. |
| 3 | * |
| 4 | * Copyright (C) 2016, Freescale Semiconductor |
| 5 | * |
| 6 | * Mingkai Hu <mingkai.hu@nxp.com> |
| 7 | * |
| 8 | * This file is licensed under the terms of the GNU General Public |
| 9 | * License version 2. This program is licensed "as is" without any |
| 10 | * warranty of any kind, whether express or implied. |
| 11 | */ |
| 12 | |
| 13 | /include/ "skeleton64.dtsi" |
| 14 | |
| 15 | / { |
| 16 | compatible = "fsl,ls1046a"; |
| 17 | interrupt-parent = <&gic>; |
| 18 | |
| 19 | sysclk: sysclk { |
| 20 | compatible = "fixed-clock"; |
| 21 | #clock-cells = <0>; |
| 22 | clock-frequency = <100000000>; |
| 23 | clock-output-names = "sysclk"; |
| 24 | }; |
| 25 | |
| 26 | gic: interrupt-controller@1400000 { |
| 27 | compatible = "arm,gic-400"; |
| 28 | #interrupt-cells = <3>; |
| 29 | interrupt-controller; |
| 30 | reg = <0x0 0x1410000 0 0x10000>, /* GICD */ |
| 31 | <0x0 0x1420000 0 0x10000>, /* GICC */ |
| 32 | <0x0 0x1440000 0 0x20000>, /* GICH */ |
| 33 | <0x0 0x1460000 0 0x20000>; /* GICV */ |
| 34 | interrupts = <1 9 0xf08>; |
| 35 | }; |
| 36 | |
| 37 | soc { |
| 38 | compatible = "simple-bus"; |
| 39 | #address-cells = <2>; |
| 40 | #size-cells = <2>; |
| 41 | ranges; |
| 42 | |
| 43 | clockgen: clocking@1ee1000 { |
| 44 | compatible = "fsl,ls1046a-clockgen"; |
| 45 | reg = <0x0 0x1ee1000 0x0 0x1000>; |
| 46 | #clock-cells = <2>; |
| 47 | clocks = <&sysclk>; |
| 48 | }; |
| 49 | |
| 50 | dspi0: dspi@2100000 { |
| 51 | compatible = "fsl,vf610-dspi"; |
| 52 | #address-cells = <1>; |
| 53 | #size-cells = <0>; |
| 54 | reg = <0x0 0x2100000 0x0 0x10000>; |
| 55 | interrupts = <0 64 0x4>; |
| 56 | clock-names = "dspi"; |
| 57 | clocks = <&clockgen 4 0>; |
| 58 | num-cs = <6>; |
| 59 | big-endian; |
| 60 | status = "disabled"; |
| 61 | }; |
| 62 | |
| 63 | dspi1: dspi@2110000 { |
| 64 | compatible = "fsl,vf610-dspi"; |
| 65 | #address-cells = <1>; |
| 66 | #size-cells = <0>; |
| 67 | reg = <0x0 0x2110000 0x0 0x10000>; |
| 68 | interrupts = <0 65 0x4>; |
| 69 | clock-names = "dspi"; |
| 70 | clocks = <&clockgen 4 0>; |
| 71 | num-cs = <6>; |
| 72 | big-endian; |
| 73 | status = "disabled"; |
| 74 | }; |
| 75 | |
| 76 | ifc: ifc@1530000 { |
| 77 | compatible = "fsl,ifc", "simple-bus"; |
| 78 | reg = <0x0 0x1530000 0x0 0x10000>; |
| 79 | interrupts = <0 43 0x4>; |
| 80 | }; |
| 81 | |
| 82 | i2c0: i2c@2180000 { |
| 83 | compatible = "fsl,vf610-i2c"; |
| 84 | #address-cells = <1>; |
| 85 | #size-cells = <0>; |
| 86 | reg = <0x0 0x2180000 0x0 0x10000>; |
| 87 | interrupts = <0 56 0x4>; |
| 88 | clock-names = "i2c"; |
| 89 | clocks = <&clockgen 4 0>; |
| 90 | status = "disabled"; |
| 91 | }; |
| 92 | |
| 93 | i2c1: i2c@2190000 { |
| 94 | compatible = "fsl,vf610-i2c"; |
| 95 | #address-cells = <1>; |
| 96 | #size-cells = <0>; |
| 97 | reg = <0x0 0x2190000 0x0 0x10000>; |
| 98 | interrupts = <0 57 0x4>; |
| 99 | clock-names = "i2c"; |
| 100 | clocks = <&clockgen 4 0>; |
| 101 | status = "disabled"; |
| 102 | }; |
| 103 | |
| 104 | i2c2: i2c@21a0000 { |
| 105 | compatible = "fsl,vf610-i2c"; |
| 106 | #address-cells = <1>; |
| 107 | #size-cells = <0>; |
| 108 | reg = <0x0 0x21a0000 0x0 0x10000>; |
| 109 | interrupts = <0 58 0x4>; |
| 110 | clock-names = "i2c"; |
| 111 | clocks = <&clockgen 4 0>; |
| 112 | status = "disabled"; |
| 113 | }; |
| 114 | |
| 115 | i2c3: i2c@21b0000 { |
| 116 | compatible = "fsl,vf610-i2c"; |
| 117 | #address-cells = <1>; |
| 118 | #size-cells = <0>; |
| 119 | reg = <0x0 0x21b0000 0x0 0x10000>; |
| 120 | interrupts = <0 59 0x4>; |
| 121 | clock-names = "i2c"; |
| 122 | clocks = <&clockgen 4 0>; |
| 123 | status = "disabled"; |
| 124 | }; |
| 125 | |
| 126 | duart0: serial@21c0500 { |
| 127 | compatible = "fsl,ns16550", "ns16550a"; |
| 128 | reg = <0x00 0x21c0500 0x0 0x100>; |
| 129 | interrupts = <0 54 0x4>; |
| 130 | clocks = <&clockgen 4 0>; |
| 131 | }; |
| 132 | |
| 133 | duart1: serial@21c0600 { |
| 134 | compatible = "fsl,ns16550", "ns16550a"; |
| 135 | reg = <0x00 0x21c0600 0x0 0x100>; |
| 136 | interrupts = <0 54 0x4>; |
| 137 | clocks = <&clockgen 4 0>; |
| 138 | }; |
| 139 | |
| 140 | duart2: serial@21d0500 { |
| 141 | compatible = "fsl,ns16550", "ns16550a"; |
| 142 | reg = <0x0 0x21d0500 0x0 0x100>; |
| 143 | interrupts = <0 55 0x4>; |
| 144 | clocks = <&clockgen 4 0>; |
| 145 | }; |
| 146 | |
| 147 | duart3: serial@21d0600 { |
| 148 | compatible = "fsl,ns16550", "ns16550a"; |
| 149 | reg = <0x0 0x21d0600 0x0 0x100>; |
| 150 | interrupts = <0 55 0x4>; |
| 151 | clocks = <&clockgen 4 0>; |
| 152 | }; |
| 153 | |
| 154 | qspi: quadspi@1550000 { |
| 155 | compatible = "fsl,vf610-qspi"; |
| 156 | #address-cells = <1>; |
| 157 | #size-cells = <0>; |
| 158 | reg = <0x0 0x1550000 0x0 0x10000>, |
| 159 | <0x0 0x40000000 0x0 0x10000000>; |
| 160 | reg-names = "QuadSPI", "QuadSPI-memory"; |
| 161 | num-cs = <4>; |
| 162 | big-endian; |
| 163 | status = "disabled"; |
| 164 | }; |
| 165 | }; |
| 166 | }; |