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Giulio Benetti85a5cd92020-01-10 15:47:04 +01001// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
2/*
3 * Copyright (C) 2019
4 * Author(s): Giulio Benetti <giulio.benetti@benettiengineering.com>
5 */
6
Giulio Benetti85a5cd92020-01-10 15:47:04 +01007#include "armv7-m.dtsi"
8#include <dt-bindings/interrupt-controller/arm-gic.h>
9#include <dt-bindings/clock/imxrt1050-clock.h>
10#include <dt-bindings/gpio/gpio.h>
11#include <dt-bindings/memory/imxrt-sdram.h>
12
13/ {
Giulio Benetti70259982020-04-08 17:11:05 +020014 #address-cells = <1>;
15 #size-cells = <1>;
16
Giulio Benetti85a5cd92020-01-10 15:47:04 +010017 aliases {
Giulio Benetti5595c002020-04-08 17:10:21 +020018 display0 = &lcdif;
Giulio Benetti85a5cd92020-01-10 15:47:04 +010019 gpio0 = &gpio1;
20 gpio1 = &gpio2;
21 gpio2 = &gpio3;
22 gpio3 = &gpio4;
23 gpio4 = &gpio5;
24 mmc0 = &usdhc1;
25 serial0 = &lpuart1;
Giulio Benetti63b49fb2021-05-20 16:10:16 +020026 usbphy0 = &usbphy1;
Giulio Benetti85a5cd92020-01-10 15:47:04 +010027 };
28
29 clocks {
Giulio Benetti37a748e2021-05-13 12:18:39 +020030 osc: osc {
Giulio Benetti85a5cd92020-01-10 15:47:04 +010031 compatible = "fsl,imx-osc", "fixed-clock";
32 #clock-cells = <0>;
33 clock-frequency = <24000000>;
34 };
35 };
36
37 soc {
Giulio Benetti85a5cd92020-01-10 15:47:04 +010038 semc: semc@402f0000 {
Giulio Benetti85a5cd92020-01-10 15:47:04 +010039 compatible = "fsl,imxrt-semc";
40 reg = <0x402f0000 0x4000>;
41 clocks = <&clks IMXRT1050_CLK_SEMC>;
42 pinctrl-0 = <&pinctrl_semc>;
43 pinctrl-names = "default";
44 status = "okay";
45 };
46
47 lpuart1: serial@40184000 {
48 compatible = "fsl,imxrt-lpuart";
49 reg = <0x40184000 0x4000>;
50 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
51 clocks = <&clks IMXRT1050_CLK_LPUART1>;
52 clock-names = "per";
53 status = "disabled";
54 };
55
56 iomuxc: iomuxc@401f8000 {
57 compatible = "fsl,imxrt-iomuxc";
58 reg = <0x401f8000 0x4000>;
59 fsl,mux_mask = <0x7>;
60 };
61
62 clks: ccm@400fc000 {
Giulio Benetti85a5cd92020-01-10 15:47:04 +010063 compatible = "fsl,imxrt1050-ccm";
64 reg = <0x400fc000 0x4000>;
65 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>,
66 <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
67 #clock-cells = <1>;
68 };
69
70 usdhc1: usdhc@402c0000 {
Giulio Benetti85a5cd92020-01-10 15:47:04 +010071 compatible = "fsl,imxrt-usdhc";
72 reg = <0x402c0000 0x10000>;
73 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
74 clocks = <&clks IMXRT1050_CLK_USDHC1>;
75 clock-names = "per";
76 bus-width = <4>;
77 fsl,tuning-start-tap = <20>;
78 fsl,tuning-step= <2>;
79 status = "disabled";
80 };
81
82 gpio1: gpio@401b8000 {
Giulio Benetti85a5cd92020-01-10 15:47:04 +010083 compatible = "fsl,imxrt-gpio", "fsl,imx35-gpio";
84 reg = <0x401b8000 0x4000>;
85 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>,
86 <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
87 gpio-controller;
88 #gpio-cells = <2>;
89 interrupt-controller;
90 #interrupt-cells = <2>;
91 };
92
93 gpio2: gpio@401bc000 {
Giulio Benetti85a5cd92020-01-10 15:47:04 +010094 compatible = "fsl,imxrt-gpio", "fsl,imx35-gpio";
95 reg = <0x401bc000 0x4000>;
96 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>,
97 <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
98 gpio-controller;
99 #gpio-cells = <2>;
100 interrupt-controller;
101 #interrupt-cells = <2>;
102 };
103
104 gpio3: gpio@401c0000 {
Giulio Benetti85a5cd92020-01-10 15:47:04 +0100105 compatible = "fsl,imxrt-gpio", "fsl,imx35-gpio";
106 reg = <0x401c0000 0x4000>;
107 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>,
108 <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
109 gpio-controller;
110 #gpio-cells = <2>;
111 interrupt-controller;
112 #interrupt-cells = <2>;
113 };
114
115 gpio4: gpio@401c4000 {
Giulio Benetti85a5cd92020-01-10 15:47:04 +0100116 compatible = "fsl,imxrt-gpio", "fsl,imx35-gpio";
117 reg = <0x401c4000 0x4000>;
118 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>,
119 <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
120 gpio-controller;
121 #gpio-cells = <2>;
122 interrupt-controller;
123 #interrupt-cells = <2>;
124 };
125
126 gpio5: gpio@400c0000 {
Giulio Benetti85a5cd92020-01-10 15:47:04 +0100127 compatible = "fsl,imxrt-gpio", "fsl,imx35-gpio";
128 reg = <0x400c0000 0x4000>;
129 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>,
130 <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
131 gpio-controller;
132 #gpio-cells = <2>;
133 interrupt-controller;
134 #interrupt-cells = <2>;
135 };
Giulio Benetti5595c002020-04-08 17:10:21 +0200136
137 lcdif: lcdif@402b8000 {
Giulio Benetti1c0cb072020-04-28 18:20:11 +0200138 compatible = "fsl,imxrt-lcdif";
139 reg = <0x402b8000 0x4000>;
140 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
Giulio Benetti586ec092021-05-13 12:19:35 +0200141 clocks = <&clks IMXRT1050_CLK_LCDIF_PIX>,
142 <&clks IMXRT1050_CLK_LCDIF_APB>;
143 clock-names = "pix", "axi";
Giulio Benettica712282021-05-13 12:19:34 +0200144 assigned-clocks = <&clks IMXRT1050_CLK_LCDIF_SEL>;
145 assigned-clock-parents = <&clks IMXRT1050_CLK_PLL5_VIDEO>;
Giulio Benetti1c0cb072020-04-28 18:20:11 +0200146 status = "disabled";
Giulio Benetti5595c002020-04-08 17:10:21 +0200147 };
Giulio Benettid61b4d42021-05-13 12:18:40 +0200148
149 gpt1: gpt1@401ec000 {
150 compatible = "fsl,imxrt-gpt";
151 reg = <0x401ec000 0x4000>;
152 interrupts = <100>;
153 clocks = <&osc>;
154 status = "disabled";
155 };
Giulio Benetti63b49fb2021-05-20 16:10:16 +0200156
157 usbphy1: usbphy@400d9000 {
158 compatible = "fsl,imxrt-usbphy";
159 reg = <0x400d9000 0x1000>;
160 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
161 };
162
163 usbmisc: usbmisc@402e0800 {
164 #index-cells = <1>;
165 compatible = "fsl,imxrt-usbmisc";
166 reg = <0x402e0800 0x200>;
167 clocks = <&clks IMXRT1050_CLK_USBOH3>;
168 };
169
170 usbotg1: usb@402e0000 {
171 compatible = "fsl,imxrt-usb", "fsl,imx27-usb";
172 reg = <0x402e0000 0x200>;
173 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
174 clocks = <&clks IMXRT1050_CLK_USBOH3>;
175 fsl,usbphy = <&usbphy1>;
176 fsl,usbmisc = <&usbmisc 0>;
177 ahb-burst-config = <0x0>;
178 tx-burst-size-dword = <0x10>;
179 rx-burst-size-dword = <0x10>;
180 status = "disabled";
181 };
Giulio Benetti85a5cd92020-01-10 15:47:04 +0100182 };
183};