| Alex Marginean | 72f3aa5 | 2021-01-27 13:00:00 +0200 | [diff] [blame] | 1 | // SPDX-License-Identifier: GPL-2.0+ OR X11 |
| 2 | /* |
| 3 | * NXP LS1028A-QDS device tree fragment for RCW 7777 |
| 4 | * |
| 5 | * Copyright 2019-2021 NXP Semiconductors |
| 6 | */ |
| 7 | |
| 8 | /* |
| 9 | * This setup is using a SCH-30841 card with AQR412 10G quad PHY. |
| 10 | * |
| 11 | * Switch ports are mapped 1:1 to AQR412 card ports seated in slot 1. |
| 12 | * Bottom port is port 0. |
| 13 | * Note that this is only usable for: |
| 14 | * - QDS boards WITHOUT lane B rework, |
| 15 | * - AQR412 card WITHOUT lane A -> lane C rework |
| 16 | * |
| 17 | * The following DTS assumes DIP SW5[1-3] = 000b. |
| 18 | */ |
| 19 | &slot1 { |
| 20 | #include "fsl-sch-30841.dtsi" |
| 21 | }; |
| 22 | |
| Vladimir Oltean | c32039a | 2021-06-29 20:53:11 +0300 | [diff] [blame] | 23 | &enetc2 { |
| 24 | status = "okay"; |
| 25 | }; |
| 26 | |
| Alex Marginean | 72f3aa5 | 2021-01-27 13:00:00 +0200 | [diff] [blame] | 27 | &mscc_felix { |
| 28 | status = "okay"; |
| 29 | }; |
| 30 | |
| 31 | &mscc_felix_port0 { |
| 32 | status = "okay"; |
| 33 | phy-mode = "sgmii-2500"; |
| 34 | phy-handle = <&{/i2c@2000000/fpga@66/mux-mdio@54/mdio@40/phy@00}>; |
| 35 | }; |
| 36 | |
| 37 | &mscc_felix_port1 { |
| 38 | status = "okay"; |
| 39 | phy-mode = "sgmii-2500"; |
| 40 | phy-handle = <&{/i2c@2000000/fpga@66/mux-mdio@54/mdio@40/phy@01}>; |
| 41 | }; |
| 42 | |
| 43 | &mscc_felix_port2 { |
| 44 | status = "okay"; |
| 45 | phy-mode = "sgmii-2500"; |
| 46 | phy-handle = <&{/i2c@2000000/fpga@66/mux-mdio@54/mdio@40/phy@02}>; |
| 47 | }; |
| 48 | |
| 49 | &mscc_felix_port3 { |
| 50 | status = "okay"; |
| 51 | phy-mode = "sgmii-2500"; |
| 52 | phy-handle = <&{/i2c@2000000/fpga@66/mux-mdio@54/mdio@40/phy@03}>; |
| 53 | }; |
| Vladimir Oltean | c32039a | 2021-06-29 20:53:11 +0300 | [diff] [blame] | 54 | |
| 55 | &mscc_felix_port4 { |
| 56 | ethernet = <&enetc2>; |
| 57 | status = "okay"; |
| 58 | }; |