Tom Rini | 10e4779 | 2018-05-06 17:58:06 -0400 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0+ */ |
Bo Shen | 06ce3f4 | 2014-02-09 15:52:39 +0800 | [diff] [blame] | 2 | /* |
3 | * Configuration settings for the SAMA5D3 Xplained board. | ||||
4 | * | ||||
5 | * Copyright (C) 2014 Atmel Corporation | ||||
6 | * Bo Shen <voice.shen@atmel.com> | ||||
Bo Shen | 06ce3f4 | 2014-02-09 15:52:39 +0800 | [diff] [blame] | 7 | */ |
8 | |||||
9 | #ifndef __CONFIG_H | ||||
10 | #define __CONFIG_H | ||||
11 | |||||
Fabien Lehoussel | 04df71a | 2020-02-24 16:45:31 +0100 | [diff] [blame] | 12 | #include <linux/sizes.h> |
Wu, Josh | 4258754 | 2015-03-30 14:51:19 +0800 | [diff] [blame] | 13 | #include "at91-sama5_common.h" |
Bo Shen | 06ce3f4 | 2014-02-09 15:52:39 +0800 | [diff] [blame] | 14 | |
Bo Shen | 06ce3f4 | 2014-02-09 15:52:39 +0800 | [diff] [blame] | 15 | /* |
16 | * This needs to be defined for the OHCI code to work but it is defined as | ||||
17 | * ATMEL_ID_UHPHS in the CPU specific header files. | ||||
18 | */ | ||||
Wenyou Yang | d19b901 | 2017-09-14 11:07:42 +0800 | [diff] [blame] | 19 | #define ATMEL_ID_UHP 32 |
Bo Shen | 06ce3f4 | 2014-02-09 15:52:39 +0800 | [diff] [blame] | 20 | |
21 | /* | ||||
22 | * Specify the clock enable bit in the PMC_SCER register. | ||||
23 | */ | ||||
Wenyou Yang | d19b901 | 2017-09-14 11:07:42 +0800 | [diff] [blame] | 24 | #define ATMEL_PMC_UHP (1 << 6) |
Bo Shen | 06ce3f4 | 2014-02-09 15:52:39 +0800 | [diff] [blame] | 25 | |
Bo Shen | 06ce3f4 | 2014-02-09 15:52:39 +0800 | [diff] [blame] | 26 | /* SDRAM */ |
Wenyou Yang | d19b901 | 2017-09-14 11:07:42 +0800 | [diff] [blame] | 27 | #define CONFIG_SYS_SDRAM_BASE 0x20000000 |
Bo Shen | 06ce3f4 | 2014-02-09 15:52:39 +0800 | [diff] [blame] | 28 | #define CONFIG_SYS_SDRAM_SIZE 0x10000000 |
29 | |||||
Bo Shen | 06ce3f4 | 2014-02-09 15:52:39 +0800 | [diff] [blame] | 30 | /* NAND flash */ |
Bo Shen | 06ce3f4 | 2014-02-09 15:52:39 +0800 | [diff] [blame] | 31 | #ifdef CONFIG_CMD_NAND |
Bo Shen | 06ce3f4 | 2014-02-09 15:52:39 +0800 | [diff] [blame] | 32 | #define CONFIG_SYS_MAX_NAND_DEVICE 1 |
Wenyou Yang | d19b901 | 2017-09-14 11:07:42 +0800 | [diff] [blame] | 33 | #define CONFIG_SYS_NAND_BASE 0x60000000 |
Bo Shen | 06ce3f4 | 2014-02-09 15:52:39 +0800 | [diff] [blame] | 34 | /* our ALE is AD21 */ |
35 | #define CONFIG_SYS_NAND_MASK_ALE (1 << 21) | ||||
36 | /* our CLE is AD22 */ | ||||
37 | #define CONFIG_SYS_NAND_MASK_CLE (1 << 22) | ||||
Tom Rini | 00448d2 | 2017-07-28 21:31:42 -0400 | [diff] [blame] | 38 | #endif |
Bo Shen | 06ce3f4 | 2014-02-09 15:52:39 +0800 | [diff] [blame] | 39 | |
Bo Shen | 735ef1a | 2014-03-19 14:48:45 +0800 | [diff] [blame] | 40 | /* SPL */ |
Bo Shen | 735ef1a | 2014-03-19 14:48:45 +0800 | [diff] [blame] | 41 | |
Fabien Lehoussel | 04df71a | 2020-02-24 16:45:31 +0100 | [diff] [blame] | 42 | /* size of u-boot.bin to load */ |
43 | #define CONFIG_SYS_MONITOR_LEN (2 * SZ_512K) | ||||
Bo Shen | 735ef1a | 2014-03-19 14:48:45 +0800 | [diff] [blame] | 44 | |
Michael Opdenacker | 6722614 | 2021-05-31 23:23:48 +0200 | [diff] [blame] | 45 | /* Falcon boot support on raw MMC */ |
Michael Opdenacker | 6722614 | 2021-05-31 23:23:48 +0200 | [diff] [blame] | 46 | /* U-Boot proper stored by default at 0x200 (256 KiB) */ |
Michael Opdenacker | 6722614 | 2021-05-31 23:23:48 +0200 | [diff] [blame] | 47 | |
Bo Shen | 735ef1a | 2014-03-19 14:48:45 +0800 | [diff] [blame] | 48 | #endif |