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git01.mediatek.com / filogic / uboot / f3bcc83675a72c34a78c517d10a31cce7dc17315 / . / board / freescale / imx8mq_evk / imx8mq_evk.c
blob: 1463e6e6963b2f767b061ac70ef3ac5f1b718737 [file] [log] [blame]
Peng Fanaeb9c062018-11-20 10:20:00 +0000[diff] [blame]1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * Copyright 2018 NXP
4 */
5
6#include <common.h>
Simon Glass5e6201b2019-08-01 09:46:51 -0600[diff] [blame]7#include <env.h>
Peng Fanaeb9c062018-11-20 10:20:00 +0000[diff] [blame]8#include <malloc.h>
9#include <errno.h>
10#include <asm/io.h>
11#include <miiphy.h>
12#include <netdev.h>
13#include <asm/mach-imx/iomux-v3.h>
14#include <asm-generic/gpio.h>
Yangbo Lu73340382019-06-21 11:42:28 +0800[diff] [blame]15#include <fsl_esdhc_imx.h>
Peng Fanaeb9c062018-11-20 10:20:00 +0000[diff] [blame]16#include <mmc.h>
17#include <asm/arch/imx8mq_pins.h>
18#include <asm/arch/sys_proto.h>
19#include <asm/mach-imx/gpio.h>
20#include <asm/mach-imx/mxc_i2c.h>
21#include <asm/arch/clock.h>
22#include <spl.h>
23#include <power/pmic.h>
24#include <power/pfuze100_pmic.h>
25#include "../common/pfuze.h"
26
27DECLARE_GLOBAL_DATA_PTR;
28
29#define UART_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_FSEL1)
30
31#define WDOG_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_HYS | PAD_CTL_PUE)
32
33static iomux_v3_cfg_t const wdog_pads[] = {
34 IMX8MQ_PAD_GPIO1_IO02__WDOG1_WDOG_B | MUX_PAD_CTRL(WDOG_PAD_CTRL),
35};
36
37static iomux_v3_cfg_t const uart_pads[] = {
38 IMX8MQ_PAD_UART1_RXD__UART1_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
39 IMX8MQ_PAD_UART1_TXD__UART1_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
40};
41
42int board_early_init_f(void)
43{
44 struct wdog_regs *wdog = (struct wdog_regs *)WDOG1_BASE_ADDR;
45
46 imx_iomux_v3_setup_multiple_pads(wdog_pads, ARRAY_SIZE(wdog_pads));
47 set_wdog_reset(wdog);
48
49 imx_iomux_v3_setup_multiple_pads(uart_pads, ARRAY_SIZE(uart_pads));
50
51 return 0;
52}
53
54int dram_init(void)
55{
56 /* rom_pointer[1] contains the size of TEE occupies */
57 if (rom_pointer[1])
58 gd->ram_size = PHYS_SDRAM_SIZE - rom_pointer[1];
59 else
60 gd->ram_size = PHYS_SDRAM_SIZE;
61
62 return 0;
63}
64
65#ifdef CONFIG_FEC_MXC
66#define FEC_RST_PAD IMX_GPIO_NR(1, 9)
67static iomux_v3_cfg_t const fec1_rst_pads[] = {
68 IMX8MQ_PAD_GPIO1_IO09__GPIO1_IO9 | MUX_PAD_CTRL(NO_PAD_CTRL),
69};
70
71static void setup_iomux_fec(void)
72{
73 imx_iomux_v3_setup_multiple_pads(fec1_rst_pads,
74 ARRAY_SIZE(fec1_rst_pads));
75
76 gpio_request(IMX_GPIO_NR(1, 9), "fec1_rst");
77 gpio_direction_output(IMX_GPIO_NR(1, 9), 0);
78 udelay(500);
79 gpio_direction_output(IMX_GPIO_NR(1, 9), 1);
80}
81
82static int setup_fec(void)
83{
84 struct iomuxc_gpr_base_regs *gpr =
85 (struct iomuxc_gpr_base_regs *)IOMUXC_GPR_BASE_ADDR;
86
87 setup_iomux_fec();
88
89 /* Use 125M anatop REF_CLK1 for ENET1, not from external */
90 clrsetbits_le32(&gpr->gpr[1], BIT(13) | BIT(17), 0);
91 return set_clk_enet(ENET_125MHZ);
92}
93
94int board_phy_config(struct phy_device *phydev)
95{
96 /* enable rgmii rxc skew and phy mode select to RGMII copper */
97 phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x1f);
98 phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x8);
99
100 phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x05);
101 phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x100);
102
103 if (phydev->drv->config)
104 phydev->drv->config(phydev);
105 return 0;
106}
107#endif
108
109int board_init(void)
110{
111#ifdef CONFIG_FEC_MXC
112 setup_fec();
113#endif
114
115 return 0;
116}
117
118int board_mmc_get_env_dev(int devno)
119{
120 return devno;
121}
122
123int board_late_init(void)
124{
125#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
126 env_set("board_name", "EVK");
127 env_set("board_rev", "iMX8MQ");
128#endif
129
130 return 0;
131}