blob: dd9421687638725cec4738a0cb94ad6abcc78740 [file] [log] [blame]
Tom Rini10e47792018-05-06 17:58:06 -04001/* SPDX-License-Identifier: GPL-2.0+ */
Vikas Manocha33913c52014-11-18 10:42:22 -08002/*
Patrice Chotardcc551162017-10-23 09:53:59 +02003 * Copyright (C) 2014, STMicroelectronics - All Rights Reserved
4 * Author(s): Vikas Manocha, <vikas.manocha@st.com> for STMicroelectronics.
Vikas Manocha33913c52014-11-18 10:42:22 -08005 */
6
7#ifndef __CONFIG_STV0991_H
8#define __CONFIG_STV0991_H
Vikas Manocha33913c52014-11-18 10:42:22 -08009#define CONFIG_SYS_EXCEPTION_VECTORS_HIGH
Vikas Manocha32b9e712014-11-18 10:42:23 -080010
Vikas Manocha33913c52014-11-18 10:42:22 -080011/* ram memory-related information */
Vikas Manocha33913c52014-11-18 10:42:22 -080012#define PHYS_SDRAM_1 0x00000000
13#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
14#define PHYS_SDRAM_1_SIZE 0x00198000
15
Vikas Manocha33913c52014-11-18 10:42:22 -080016/* user interface */
Vikas Manocha7f34a692014-11-18 10:42:24 -080017#define CONFIG_SYS_CBSIZE 1024
Vikas Manocha33913c52014-11-18 10:42:22 -080018
19/* MISC */
Vikas Manochad70864c2014-12-01 12:27:53 -080020#define CONFIG_SYS_INIT_RAM_SIZE 0x8000
Vikas Manocha33913c52014-11-18 10:42:22 -080021#define CONFIG_SYS_INIT_RAM_ADDR 0x00190000
22#define CONFIG_SYS_INIT_SP_OFFSET \
23 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
Bin Meng75574052016-02-05 19:30:11 -080024/* U-Boot Load Address */
Vikas Manocha33913c52014-11-18 10:42:22 -080025#define CONFIG_SYS_INIT_SP_ADDR \
26 (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
27
Vikas Manocha32b9e712014-11-18 10:42:23 -080028/* GMAC related configs */
29
Vikas Manocha32b9e712014-11-18 10:42:23 -080030#define CONFIG_DW_ALTDESCRIPTOR
Vikas Manocha32b9e712014-11-18 10:42:23 -080031
32/* Command support defines */
Vikas Manocha32b9e712014-11-18 10:42:23 -080033#define CONFIG_PHY_RESET_DELAY 10000 /* in usec */
34
Vikas Manocha7f34a692014-11-18 10:42:24 -080035/* Misc configuration */
Vikas Manocha7f34a692014-11-18 10:42:24 -080036
Vikas Manocha8cc062f2015-07-02 18:29:41 -070037/*
38+ * QSPI support
39+ */
40#ifdef CONFIG_OF_CONTROL /* QSPI is controlled via DT */
Vikas Manocha8cc062f2015-07-02 18:29:41 -070041#define CONFIG_CQSPI_REF_CLK ((30/4)/2)*1000*1000
Vikas Manocha8cc062f2015-07-02 18:29:41 -070042
Vikas Manocha8cc062f2015-07-02 18:29:41 -070043#endif
44
Vikas Manocha33913c52014-11-18 10:42:22 -080045#endif /* __CONFIG_H */