blob: 8bfd1fcd25a8eb5f206c5990abfa5eb990f8a095 [file] [log] [blame]
Tom Rini10e47792018-05-06 17:58:06 -04001/* SPDX-License-Identifier: GPL-2.0+ */
Heiko Schocher44a93442015-06-29 09:10:48 +02002/*
3 * (C) Copyright 2007-2008
4 * Stelian Pop <stelian@popies.net>
5 * Lead Tech Design <www.leadtechdesign.com>
6 *
7 * (C) Copyright 2010
8 * Achim Ehrlich <aehrlich@taskit.de>
9 * taskit GmbH <www.taskit.de>
10 *
11 * (C) Copyright 2012
12 * Markus Hubig <mhubig@imko.de>
13 * IMKO GmbH <www.imko.de>
14 *
15 * (C) Copyright 2014
16 * Heiko Schocher <hs@denx.de>
17 * DENX Software Engineering GmbH
18 *
19 * Configuation settings for the smartweb.
Heiko Schocher44a93442015-06-29 09:10:48 +020020 */
21
22#ifndef __CONFIG_H
23#define __CONFIG_H
24
25/*
26 * SoC must be defined first, before hardware.h is included.
27 * In this case SoC is defined in boards.cfg.
28 */
29#include <asm/hardware.h>
Heiko Schochercf5137c2015-09-08 11:52:52 +020030#include <linux/sizes.h>
Heiko Schocher44a93442015-06-29 09:10:48 +020031
32/*
33 * Warning: changing CONFIG_SYS_TEXT_BASE requires adapting the initial boot
34 * program. Since the linker has to swallow that define, we must use a pure
35 * hex number here!
36 */
Heiko Schocher44a93442015-06-29 09:10:48 +020037
38/* ARM asynchronous clock */
39#define CONFIG_SYS_AT91_SLOW_CLOCK 32768 /* slow clock xtal */
40#define CONFIG_SYS_AT91_MAIN_CLOCK 18432000 /* 18.432MHz crystal */
41
42/* misc settings */
Heiko Schocher44a93442015-06-29 09:10:48 +020043
Matthias Michel0ae5e922016-01-27 15:56:07 +010044/* We set the max number of command args high to avoid HUSH bugs. */
45#define CONFIG_SYS_MAXARGS 32
46
Heiko Schocher44a93442015-06-29 09:10:48 +020047/* setting board specific options */
Matthias Michel0ae5e922016-01-27 15:56:07 +010048#define CONFIG_SYS_AUTOLOAD "yes"
49#define CONFIG_RESET_TO_RETRY
Heiko Schocher44a93442015-06-29 09:10:48 +020050
51/* The LED PINs */
52#define CONFIG_RED_LED AT91_PIN_PA9
53#define CONFIG_GREEN_LED AT91_PIN_PA6
54
55/*
56 * SDRAM: 1 bank, 64 MB, base address 0x20000000
57 * Already initialized before u-boot gets started.
58 */
Heiko Schocher44a93442015-06-29 09:10:48 +020059#define CONFIG_SYS_SDRAM_BASE ATMEL_BASE_CS1
Heiko Schochercf5137c2015-09-08 11:52:52 +020060#define CONFIG_SYS_SDRAM_SIZE (64 * SZ_1M)
Heiko Schocher44a93442015-06-29 09:10:48 +020061
62/*
63 * Perform a SDRAM Memtest from the start of SDRAM
64 * till the beginning of the U-Boot position in RAM.
65 */
Heiko Schocher44a93442015-06-29 09:10:48 +020066
Heiko Schocher44a93442015-06-29 09:10:48 +020067/* NAND flash settings */
Heiko Schocher44a93442015-06-29 09:10:48 +020068#define CONFIG_SYS_MAX_NAND_DEVICE 1
69#define CONFIG_SYS_NAND_BASE ATMEL_BASE_CS3
70#define CONFIG_SYS_NAND_DBW_8
71#define CONFIG_SYS_NAND_MASK_ALE (1 << 21)
72#define CONFIG_SYS_NAND_MASK_CLE (1 << 22)
73#define CONFIG_SYS_NAND_ENABLE_PIN AT91_PIN_PC14
74#define CONFIG_SYS_NAND_READY_PIN AT91_PIN_PC13
75
Heiko Schocher44a93442015-06-29 09:10:48 +020076/* general purpose I/O */
77#define CONFIG_ATMEL_LEGACY /* required until (g)pio is fixed */
Heiko Schocher44a93442015-06-29 09:10:48 +020078#define CONFIG_AT91_GPIO_PULLUP 1 /* keep pullups on peripheral pins */
79
80/* serial console */
Heiko Schocher44a93442015-06-29 09:10:48 +020081#define CONFIG_USART_BASE ATMEL_BASE_DBGU
82#define CONFIG_USART_ID ATMEL_ID_SYS
Heiko Schocher44a93442015-06-29 09:10:48 +020083
84/*
85 * Ethernet configuration
86 *
87 */
Heiko Schocher44a93442015-06-29 09:10:48 +020088#define CONFIG_RMII /* use reduced MII inteface */
89#define CONFIG_NET_RETRY_COUNT 20 /* # of DHCP/BOOTP retries */
90#define CONFIG_AT91_WANTS_COMMON_PHY
91
92/* BOOTP and DHCP options */
93#define CONFIG_BOOTP_BOOTFILESIZE
Heiko Schocher44a93442015-06-29 09:10:48 +020094
Heiko Schocher44a93442015-06-29 09:10:48 +020095#if !defined(CONFIG_SPL_BUILD)
96/* USB configuration */
97#define CONFIG_USB_ATMEL
98#define CONFIG_USB_ATMEL_CLK_SEL_PLLB
99#define CONFIG_USB_OHCI_NEW
Heiko Schocher44a93442015-06-29 09:10:48 +0200100#define CONFIG_SYS_USB_OHCI_CPU_INIT
101#define CONFIG_SYS_USB_OHCI_REGS_BASE ATMEL_UHP_BASE
102#define CONFIG_SYS_USB_OHCI_SLOT_NAME "at91sam9260"
103#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2
Heiko Schochercf5137c2015-09-08 11:52:52 +0200104
Heiko Schochercf5137c2015-09-08 11:52:52 +0200105/* USB DFU support */
Heiko Schochercf5137c2015-09-08 11:52:52 +0200106
Heiko Schochercf5137c2015-09-08 11:52:52 +0200107#define CONFIG_USB_GADGET_AT91
108
109/* DFU class support */
Heiko Schochercf5137c2015-09-08 11:52:52 +0200110#define DFU_MANIFEST_POLL_TIMEOUT 25000
Heiko Schocher44a93442015-06-29 09:10:48 +0200111#endif
112
113/* General Boot Parameter */
Heiko Schocher44a93442015-06-29 09:10:48 +0200114#define CONFIG_SYS_CBSIZE 512
Heiko Schocher44a93442015-06-29 09:10:48 +0200115
116/*
Heiko Schocher44a93442015-06-29 09:10:48 +0200117 * The NAND Flash partitions:
118 */
Heiko Schochercf5137c2015-09-08 11:52:52 +0200119#define CONFIG_ENV_RANGE (SZ_512K)
Heiko Schocher44a93442015-06-29 09:10:48 +0200120
121/*
122 * Predefined environment variables.
123 * Usefull to define some easy to use boot commands.
124 */
125#define CONFIG_EXTRA_ENV_SETTINGS \
126 \
127 "basicargs=console=ttyS0,115200\0" \
128 \
Tom Rini5ad8e112017-10-22 17:55:07 -0400129 "mtdparts="CONFIG_MTDPARTS_DEFAULT"\0"
Heiko Schocher44a93442015-06-29 09:10:48 +0200130
Heiko Schocher44a93442015-06-29 09:10:48 +0200131#ifdef CONFIG_SPL_BUILD
132#define CONFIG_SYS_INIT_SP_ADDR 0x301000
Heiko Schocher44a93442015-06-29 09:10:48 +0200133#else
134/*
135 * Initial stack pointer: 4k - GENERATED_GBL_DATA_SIZE in internal SRAM,
136 * leaving the correct space for initial global data structure above that
137 * address while providing maximum stack area below.
138 */
139#define CONFIG_SYS_INIT_SP_ADDR \
140 (ATMEL_BASE_SRAM1 + 0x1000 - GENERATED_GBL_DATA_SIZE)
141#endif
142
Heiko Schocher44a93442015-06-29 09:10:48 +0200143/* Defines for SPL */
Heiko Schochercf5137c2015-09-08 11:52:52 +0200144#define CONFIG_SPL_MAX_SIZE (SZ_4K)
Heiko Schocher44a93442015-06-29 09:10:48 +0200145
146#define CONFIG_SPL_BSS_START_ADDR CONFIG_SYS_SDRAM_BASE
Heiko Schochercf5137c2015-09-08 11:52:52 +0200147#define CONFIG_SPL_BSS_MAX_SIZE (SZ_16K)
Heiko Schocher44a93442015-06-29 09:10:48 +0200148#define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SPL_BSS_START_ADDR + \
149 CONFIG_SPL_BSS_MAX_SIZE)
150#define CONFIG_SYS_SPL_MALLOC_SIZE CONFIG_SYS_MALLOC_LEN
Heiko Schocher44a93442015-06-29 09:10:48 +0200151
Heiko Schocher44a93442015-06-29 09:10:48 +0200152#define CONFIG_SYS_NAND_ENABLE_PIN_SPL (2*32 + 14)
Heiko Schocher44a93442015-06-29 09:10:48 +0200153#define CONFIG_SYS_USE_NANDFLASH 1
Heiko Schocher44a93442015-06-29 09:10:48 +0200154#define CONFIG_SPL_NAND_RAW_ONLY
155#define CONFIG_SPL_NAND_SOFTECC
Heiko Schochercf5137c2015-09-08 11:52:52 +0200156#define CONFIG_SYS_NAND_U_BOOT_SIZE SZ_512K
Heiko Schocher44a93442015-06-29 09:10:48 +0200157#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE
158#define CONFIG_SYS_NAND_U_BOOT_DST CONFIG_SYS_TEXT_BASE
Heiko Schocher44a93442015-06-29 09:10:48 +0200159
Heiko Schochercf5137c2015-09-08 11:52:52 +0200160#define CONFIG_SYS_NAND_SIZE (SZ_256M)
Heiko Schocher44a93442015-06-29 09:10:48 +0200161#define CONFIG_SYS_NAND_ECCSIZE 256
162#define CONFIG_SYS_NAND_ECCBYTES 3
Heiko Schocher44a93442015-06-29 09:10:48 +0200163#define CONFIG_SYS_NAND_ECCPOS { 40, 41, 42, 43, 44, 45, 46, 47, \
164 48, 49, 50, 51, 52, 53, 54, 55, \
165 56, 57, 58, 59, 60, 61, 62, 63, }
166
167#define CONFIG_SPL_ATMEL_SIZE
168#define CONFIG_SYS_MASTER_CLOCK (198656000/2)
169#define AT91_PLL_LOCK_TIMEOUT 1000000
170#define CONFIG_SYS_AT91_PLLA 0x2060bf09
171#define CONFIG_SYS_MCKR 0x100
172#define CONFIG_SYS_MCKR_CSS (0x02 | CONFIG_SYS_MCKR)
173#define CONFIG_SYS_AT91_PLLB 0x10483f0e
174
Stefan Roese67bcbef2019-04-02 10:57:25 +0200175#define CONFIG_SPL_PAD_TO CONFIG_SYS_NAND_U_BOOT_OFFS
176#define CONFIG_SYS_SPL_LEN CONFIG_SPL_PAD_TO
177
Heiko Schocher44a93442015-06-29 09:10:48 +0200178#endif /* __CONFIG_H */