Tom Rini | 10e4779 | 2018-05-06 17:58:06 -0400 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0+ */ |
Ilko Iliev | 61fdb73 | 2009-06-12 21:20:39 +0200 | [diff] [blame] | 2 | /* |
| 3 | * (C) Copyright 2007-2008 |
Stelian Pop | 5ee0c7f | 2011-11-01 00:00:39 +0100 | [diff] [blame] | 4 | * Stelian Pop <stelian@popies.net> |
Ilko Iliev | 61fdb73 | 2009-06-12 21:20:39 +0200 | [diff] [blame] | 5 | * Lead Tech Design <www.leadtechdesign.com> |
| 6 | * Ilko Iliev <www.ronetix.at> |
| 7 | * |
| 8 | * Configuation settings for the RONETIX PM9261 board. |
Ilko Iliev | 61fdb73 | 2009-06-12 21:20:39 +0200 | [diff] [blame] | 9 | */ |
| 10 | |
| 11 | #ifndef __CONFIG_H |
| 12 | #define __CONFIG_H |
| 13 | |
Asen Dimov | 6a59514 | 2011-07-26 04:48:41 +0000 | [diff] [blame] | 14 | /* |
| 15 | * SoC must be defined first, before hardware.h is included. |
| 16 | * In this case SoC is defined in boards.cfg. |
| 17 | */ |
| 18 | |
| 19 | #include <asm/hardware.h> |
Ilko Iliev | 61fdb73 | 2009-06-12 21:20:39 +0200 | [diff] [blame] | 20 | /* ARM asynchronous clock */ |
Ilko Iliev | 61fdb73 | 2009-06-12 21:20:39 +0200 | [diff] [blame] | 21 | |
Ilko Iliev | 61fdb73 | 2009-06-12 21:20:39 +0200 | [diff] [blame] | 22 | #define MASTER_PLL_DIV 15 |
| 23 | #define MASTER_PLL_MUL 162 |
| 24 | #define MAIN_PLL_DIV 2 |
Asen Dimov | 6a59514 | 2011-07-26 04:48:41 +0000 | [diff] [blame] | 25 | #define CONFIG_SYS_AT91_SLOW_CLOCK 32768 /* slow clock xtal */ |
Achim Ehrlich | 443873d | 2010-02-24 10:29:16 +0100 | [diff] [blame] | 26 | #define CONFIG_SYS_AT91_MAIN_CLOCK 18432000 |
Ilko Iliev | 61fdb73 | 2009-06-12 21:20:39 +0200 | [diff] [blame] | 27 | |
Ilko Iliev | 61fdb73 | 2009-06-12 21:20:39 +0200 | [diff] [blame] | 28 | /* clocks */ |
| 29 | /* CKGR_MOR - enable main osc. */ |
| 30 | #define CONFIG_SYS_MOR_VAL \ |
Asen Dimov | 9128acd | 2010-04-06 16:18:04 +0300 | [diff] [blame] | 31 | (AT91_PMC_MOR_MOSCEN | \ |
Ilko Iliev | 61fdb73 | 2009-06-12 21:20:39 +0200 | [diff] [blame] | 32 | (255 << 8)) /* Main Oscillator Start-up Time */ |
| 33 | #define CONFIG_SYS_PLLAR_VAL \ |
Asen Dimov | 9128acd | 2010-04-06 16:18:04 +0300 | [diff] [blame] | 34 | (AT91_PMC_PLLAR_29 | /* Bit 29 must be 1 when prog */ \ |
| 35 | AT91_PMC_PLLXR_OUT(3) | \ |
Ilko Iliev | 61fdb73 | 2009-06-12 21:20:39 +0200 | [diff] [blame] | 36 | ((MASTER_PLL_MUL - 1) << 16) | (MASTER_PLL_DIV)) |
| 37 | |
| 38 | /* PCK/2 = MCK Master Clock from PLLA */ |
| 39 | #define CONFIG_SYS_MCKR1_VAL \ |
Asen Dimov | 9128acd | 2010-04-06 16:18:04 +0300 | [diff] [blame] | 40 | (AT91_PMC_MCKR_CSS_SLOW | \ |
| 41 | AT91_PMC_MCKR_PRES_1 | \ |
Bo Shen | e55550e | 2013-11-15 11:12:33 +0800 | [diff] [blame] | 42 | AT91_PMC_MCKR_MDIV_2) |
Ilko Iliev | 61fdb73 | 2009-06-12 21:20:39 +0200 | [diff] [blame] | 43 | |
| 44 | /* PCK/2 = MCK Master Clock from PLLA */ |
| 45 | #define CONFIG_SYS_MCKR2_VAL \ |
Asen Dimov | 9128acd | 2010-04-06 16:18:04 +0300 | [diff] [blame] | 46 | (AT91_PMC_MCKR_CSS_PLLA | \ |
| 47 | AT91_PMC_MCKR_PRES_1 | \ |
Bo Shen | e55550e | 2013-11-15 11:12:33 +0800 | [diff] [blame] | 48 | AT91_PMC_MCKR_MDIV_2) |
Ilko Iliev | 61fdb73 | 2009-06-12 21:20:39 +0200 | [diff] [blame] | 49 | |
| 50 | /* define PDC[31:16] as DATA[31:16] */ |
| 51 | #define CONFIG_SYS_PIOC_PDR_VAL1 0xFFFF0000 |
| 52 | /* no pull-up for D[31:16] */ |
| 53 | #define CONFIG_SYS_PIOC_PPUDR_VAL 0xFFFF0000 |
| 54 | |
| 55 | /* EBI_CSA, no pull-ups for D[15:0], CS1 SDRAM, CS3 NAND Flash */ |
| 56 | #define CONFIG_SYS_MATRIX_EBICSA_VAL \ |
Asen Dimov | 9128acd | 2010-04-06 16:18:04 +0300 | [diff] [blame] | 57 | (AT91_MATRIX_CSA_DBPUC | AT91_MATRIX_CSA_EBI_CS1A) |
Ilko Iliev | 61fdb73 | 2009-06-12 21:20:39 +0200 | [diff] [blame] | 58 | |
| 59 | /* SDRAM */ |
| 60 | /* SDRAMC_MR Mode register */ |
| 61 | #define CONFIG_SYS_SDRC_MR_VAL1 AT91_SDRAMC_MODE_NORMAL |
| 62 | /* SDRAMC_TR - Refresh Timer register */ |
| 63 | #define CONFIG_SYS_SDRC_TR_VAL1 0x13C |
| 64 | /* SDRAMC_CR - Configuration register*/ |
| 65 | #define CONFIG_SYS_SDRC_CR_VAL \ |
| 66 | (AT91_SDRAMC_NC_9 | \ |
| 67 | AT91_SDRAMC_NR_13 | \ |
| 68 | AT91_SDRAMC_NB_4 | \ |
| 69 | AT91_SDRAMC_CAS_3 | \ |
| 70 | AT91_SDRAMC_DBW_32 | \ |
| 71 | (1 << 8) | /* Write Recovery Delay */ \ |
| 72 | (7 << 12) | /* Row Cycle Delay */ \ |
| 73 | (3 << 16) | /* Row Precharge Delay */ \ |
| 74 | (2 << 20) | /* Row to Column Delay */ \ |
| 75 | (5 << 24) | /* Active to Precharge Delay */ \ |
| 76 | (1 << 28)) /* Exit Self Refresh to Active Delay */ |
| 77 | |
| 78 | /* Memory Device Register -> SDRAM */ |
| 79 | #define CONFIG_SYS_SDRC_MDR_VAL AT91_SDRAMC_MD_SDRAM |
| 80 | #define CONFIG_SYS_SDRC_MR_VAL2 AT91_SDRAMC_MODE_PRECHARGE |
| 81 | #define CONFIG_SYS_SDRAM_VAL1 0 /* SDRAM_BASE */ |
| 82 | #define CONFIG_SYS_SDRC_MR_VAL3 AT91_SDRAMC_MODE_REFRESH |
| 83 | #define CONFIG_SYS_SDRAM_VAL2 0 /* SDRAM_BASE */ |
| 84 | #define CONFIG_SYS_SDRAM_VAL3 0 /* SDRAM_BASE */ |
| 85 | #define CONFIG_SYS_SDRAM_VAL4 0 /* SDRAM_BASE */ |
| 86 | #define CONFIG_SYS_SDRAM_VAL5 0 /* SDRAM_BASE */ |
| 87 | #define CONFIG_SYS_SDRAM_VAL6 0 /* SDRAM_BASE */ |
| 88 | #define CONFIG_SYS_SDRAM_VAL7 0 /* SDRAM_BASE */ |
| 89 | #define CONFIG_SYS_SDRAM_VAL8 0 /* SDRAM_BASE */ |
| 90 | #define CONFIG_SYS_SDRAM_VAL9 0 /* SDRAM_BASE */ |
| 91 | #define CONFIG_SYS_SDRC_MR_VAL4 AT91_SDRAMC_MODE_LMR |
| 92 | #define CONFIG_SYS_SDRAM_VAL10 0 /* SDRAM_BASE */ |
| 93 | #define CONFIG_SYS_SDRC_MR_VAL5 AT91_SDRAMC_MODE_NORMAL |
| 94 | #define CONFIG_SYS_SDRAM_VAL11 0 /* SDRAM_BASE */ |
| 95 | #define CONFIG_SYS_SDRC_TR_VAL2 1200 /* SDRAM_TR */ |
| 96 | #define CONFIG_SYS_SDRAM_VAL12 0 /* SDRAM_BASE */ |
| 97 | |
| 98 | /* setup SMC0, CS0 (NOR Flash) - 16-bit, 15 WS */ |
| 99 | #define CONFIG_SYS_SMC0_SETUP0_VAL \ |
Asen Dimov | 9128acd | 2010-04-06 16:18:04 +0300 | [diff] [blame] | 100 | (AT91_SMC_SETUP_NWE(10) | AT91_SMC_SETUP_NCS_WR(10) | \ |
| 101 | AT91_SMC_SETUP_NRD(10) | AT91_SMC_SETUP_NCS_RD(10)) |
Ilko Iliev | 61fdb73 | 2009-06-12 21:20:39 +0200 | [diff] [blame] | 102 | #define CONFIG_SYS_SMC0_PULSE0_VAL \ |
Asen Dimov | 9128acd | 2010-04-06 16:18:04 +0300 | [diff] [blame] | 103 | (AT91_SMC_PULSE_NWE(11) | AT91_SMC_PULSE_NCS_WR(11) | \ |
| 104 | AT91_SMC_PULSE_NRD(11) | AT91_SMC_PULSE_NCS_RD(11)) |
Ilko Iliev | 61fdb73 | 2009-06-12 21:20:39 +0200 | [diff] [blame] | 105 | #define CONFIG_SYS_SMC0_CYCLE0_VAL \ |
Asen Dimov | 9128acd | 2010-04-06 16:18:04 +0300 | [diff] [blame] | 106 | (AT91_SMC_CYCLE_NWE(22) | AT91_SMC_CYCLE_NRD(22)) |
Ilko Iliev | 61fdb73 | 2009-06-12 21:20:39 +0200 | [diff] [blame] | 107 | #define CONFIG_SYS_SMC0_MODE0_VAL \ |
Asen Dimov | 9128acd | 2010-04-06 16:18:04 +0300 | [diff] [blame] | 108 | (AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE | \ |
| 109 | AT91_SMC_MODE_DBW_16 | \ |
| 110 | AT91_SMC_MODE_TDF | \ |
| 111 | AT91_SMC_MODE_TDF_CYCLE(6)) |
Ilko Iliev | 61fdb73 | 2009-06-12 21:20:39 +0200 | [diff] [blame] | 112 | |
| 113 | /* user reset enable */ |
| 114 | #define CONFIG_SYS_RSTC_RMR_VAL \ |
| 115 | (AT91_RSTC_KEY | \ |
Asen Dimov | 9128acd | 2010-04-06 16:18:04 +0300 | [diff] [blame] | 116 | AT91_RSTC_CR_PROCRST | \ |
| 117 | AT91_RSTC_MR_ERSTL(1) | \ |
| 118 | AT91_RSTC_MR_ERSTL(2)) |
Ilko Iliev | 61fdb73 | 2009-06-12 21:20:39 +0200 | [diff] [blame] | 119 | |
| 120 | /* Disable Watchdog */ |
| 121 | #define CONFIG_SYS_WDTC_WDMR_VAL \ |
Asen Dimov | 9128acd | 2010-04-06 16:18:04 +0300 | [diff] [blame] | 122 | (AT91_WDT_MR_WDIDLEHLT | AT91_WDT_MR_WDDBGHLT | \ |
| 123 | AT91_WDT_MR_WDV(0xfff) | \ |
| 124 | AT91_WDT_MR_WDDIS | \ |
| 125 | AT91_WDT_MR_WDD(0xfff)) |
Ilko Iliev | 61fdb73 | 2009-06-12 21:20:39 +0200 | [diff] [blame] | 126 | |
Ilko Iliev | 61fdb73 | 2009-06-12 21:20:39 +0200 | [diff] [blame] | 127 | /* |
| 128 | * Hardware drivers |
| 129 | */ |
Ilko Iliev | 61fdb73 | 2009-06-12 21:20:39 +0200 | [diff] [blame] | 130 | |
| 131 | /* LCD */ |
Ilko Iliev | 61fdb73 | 2009-06-12 21:20:39 +0200 | [diff] [blame] | 132 | #define LCD_BPP LCD_COLOR8 |
| 133 | #define CONFIG_LCD_LOGO 1 |
| 134 | #undef LCD_TEST_PATTERN |
| 135 | #define CONFIG_LCD_INFO 1 |
| 136 | #define CONFIG_LCD_INFO_BELOW_LOGO 1 |
Ilko Iliev | 61fdb73 | 2009-06-12 21:20:39 +0200 | [diff] [blame] | 137 | #define CONFIG_ATMEL_LCD 1 |
| 138 | #define CONFIG_ATMEL_LCD_BGR555 1 |
Ilko Iliev | 61fdb73 | 2009-06-12 21:20:39 +0200 | [diff] [blame] | 139 | |
Ilko Iliev | 61fdb73 | 2009-06-12 21:20:39 +0200 | [diff] [blame] | 140 | /* |
| 141 | * BOOTP options |
| 142 | */ |
| 143 | #define CONFIG_BOOTP_BOOTFILESIZE 1 |
Ilko Iliev | 61fdb73 | 2009-06-12 21:20:39 +0200 | [diff] [blame] | 144 | |
Ilko Iliev | 61fdb73 | 2009-06-12 21:20:39 +0200 | [diff] [blame] | 145 | /* SDRAM */ |
Ilko Iliev | 61fdb73 | 2009-06-12 21:20:39 +0200 | [diff] [blame] | 146 | #define PHYS_SDRAM 0x20000000 |
| 147 | #define PHYS_SDRAM_SIZE 0x04000000 /* 64 megs */ |
| 148 | |
Ilko Iliev | 61fdb73 | 2009-06-12 21:20:39 +0200 | [diff] [blame] | 149 | /* NAND flash */ |
Ilko Iliev | 61fdb73 | 2009-06-12 21:20:39 +0200 | [diff] [blame] | 150 | #define CONFIG_SYS_MAX_NAND_DEVICE 1 |
| 151 | #define CONFIG_SYS_NAND_BASE 0x40000000 |
| 152 | #define CONFIG_SYS_NAND_DBW_8 1 |
| 153 | /* our ALE is AD22 */ |
| 154 | #define CONFIG_SYS_NAND_MASK_ALE (1 << 22) |
| 155 | /* our CLE is AD21 */ |
| 156 | #define CONFIG_SYS_NAND_MASK_CLE (1 << 21) |
Andreas Bießmann | a4c24d3 | 2013-11-29 12:13:45 +0100 | [diff] [blame] | 157 | #define CONFIG_SYS_NAND_ENABLE_PIN GPIO_PIN_PC(14) |
| 158 | #define CONFIG_SYS_NAND_READY_PIN GPIO_PIN_PA(16) |
Ilko Iliev | 61fdb73 | 2009-06-12 21:20:39 +0200 | [diff] [blame] | 159 | |
Ilko Iliev | 61fdb73 | 2009-06-12 21:20:39 +0200 | [diff] [blame] | 160 | /* NOR flash */ |
Ilko Iliev | 61fdb73 | 2009-06-12 21:20:39 +0200 | [diff] [blame] | 161 | #define PHYS_FLASH_1 0x10000000 |
| 162 | #define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1 |
| 163 | #define CONFIG_SYS_MAX_FLASH_SECT 256 |
Ilko Iliev | 61fdb73 | 2009-06-12 21:20:39 +0200 | [diff] [blame] | 164 | |
Ilko Iliev | 61fdb73 | 2009-06-12 21:20:39 +0200 | [diff] [blame] | 165 | /* USB */ |
| 166 | #define CONFIG_USB_ATMEL |
Bo Shen | 4a985df | 2013-10-21 16:14:00 +0800 | [diff] [blame] | 167 | #define CONFIG_USB_ATMEL_CLK_SEL_PLLB |
Ilko Iliev | 61fdb73 | 2009-06-12 21:20:39 +0200 | [diff] [blame] | 168 | #define CONFIG_USB_OHCI_NEW 1 |
Ilko Iliev | 61fdb73 | 2009-06-12 21:20:39 +0200 | [diff] [blame] | 169 | #define CONFIG_SYS_USB_OHCI_CPU_INIT 1 |
| 170 | #define CONFIG_SYS_USB_OHCI_REGS_BASE 0x00500000 |
| 171 | #define CONFIG_SYS_USB_OHCI_SLOT_NAME "at91sam9261" |
| 172 | #define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2 |
Ilko Iliev | 61fdb73 | 2009-06-12 21:20:39 +0200 | [diff] [blame] | 173 | |
Ilko Iliev | 61fdb73 | 2009-06-12 21:20:39 +0200 | [diff] [blame] | 174 | #undef CONFIG_SYS_USE_DATAFLASH_CS0 |
| 175 | #undef CONFIG_SYS_USE_NANDFLASH |
| 176 | #define CONFIG_SYS_USE_FLASH 1 |
| 177 | |
| 178 | #ifdef CONFIG_SYS_USE_DATAFLASH_CS0 |
| 179 | |
| 180 | /* bootstrap + u-boot + env + linux in dataflash on CS0 */ |
Ilko Iliev | 61fdb73 | 2009-06-12 21:20:39 +0200 | [diff] [blame] | 181 | |
| 182 | #elif defined(CONFIG_SYS_USE_NANDFLASH) /* CONFIG_SYS_USE_NANDFLASH */ |
| 183 | |
| 184 | /* bootstrap + u-boot + env + linux in nandflash */ |
Ilko Iliev | 61fdb73 | 2009-06-12 21:20:39 +0200 | [diff] [blame] | 185 | |
| 186 | #elif defined (CONFIG_SYS_USE_FLASH) |
Ilko Iliev | 61fdb73 | 2009-06-12 21:20:39 +0200 | [diff] [blame] | 187 | /* JFFS Partition offset set */ |
| 188 | #define CONFIG_SYS_JFFS2_FIRST_BANK 0 |
| 189 | #define CONFIG_SYS_JFFS2_NUM_BANKS 1 |
| 190 | |
| 191 | /* 512k reserved for u-boot */ |
| 192 | #define CONFIG_SYS_JFFS2_FIRST_SECTOR 11 |
| 193 | |
Ilko Iliev | 61fdb73 | 2009-06-12 21:20:39 +0200 | [diff] [blame] | 194 | #define CONFIG_CON_ROT "fbcon=rotate:3 " |
Ilko Iliev | 61fdb73 | 2009-06-12 21:20:39 +0200 | [diff] [blame] | 195 | |
| 196 | #define CONFIG_EXTRA_ENV_SETTINGS \ |
Tom Rini | 5ad8e11 | 2017-10-22 17:55:07 -0400 | [diff] [blame] | 197 | "mtdids=" CONFIG_MTDIDS_DEFAULT "\0" \ |
| 198 | "mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0" \ |
Ilko Iliev | 61fdb73 | 2009-06-12 21:20:39 +0200 | [diff] [blame] | 199 | "partition=nand0,0\0" \ |
| 200 | "ramargs=setenv bootargs $(bootargs) $(mtdparts)\0" \ |
| 201 | "nfsargs=setenv bootargs root=/dev/nfs rw " \ |
| 202 | CONFIG_CON_ROT \ |
| 203 | "nfsroot=$(serverip):$(rootpath) $(mtdparts)\0" \ |
| 204 | "addip=setenv bootargs $(bootargs) " \ |
| 205 | "ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask)"\ |
| 206 | ":$(hostname):eth0:off\0" \ |
| 207 | "ramboot=tftpboot 0x22000000 vmImage;" \ |
| 208 | "run ramargs;run addip;bootm 22000000\0" \ |
| 209 | "nfsboot=tftpboot 0x22000000 vmImage;" \ |
| 210 | "run nfsargs;run addip;bootm 22000000\0" \ |
| 211 | "flashboot=run ramargs;run addip;bootm 0x10050000\0" \ |
| 212 | "" |
| 213 | #else |
| 214 | #error "Undefined memory device" |
| 215 | #endif |
| 216 | |
Asen Dimov | 5aae746 | 2010-12-12 12:41:30 +0200 | [diff] [blame] | 217 | #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM |
Wenyou.Yang@microchip.com | 8f2bbde | 2017-07-21 17:04:56 +0800 | [diff] [blame] | 218 | #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 16 * 1024 - \ |
Asen Dimov | 5aae746 | 2010-12-12 12:41:30 +0200 | [diff] [blame] | 219 | GENERATED_GBL_DATA_SIZE) |
| 220 | |
Ilko Iliev | 61fdb73 | 2009-06-12 21:20:39 +0200 | [diff] [blame] | 221 | #endif |