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Tom Rini10e47792018-05-06 17:58:06 -04001/* SPDX-License-Identifier: GPL-2.0+ */
Thomas Abrahamd23cb312016-04-23 22:18:13 +05302/*
3 * Configuration settings for the Espresso7420 board.
4 * Copyright (C) 2016 Samsung Electronics
5 * Thomas Abraham <thomas.ab@samsung.com>
Thomas Abrahamd23cb312016-04-23 22:18:13 +05306 */
7
8#ifndef __CONFIG_EXYNOS7420_COMMON_H
9#define __CONFIG_EXYNOS7420_COMMON_H
10
11/* High Level Configuration Options */
12#define CONFIG_SAMSUNG /* in a SAMSUNG core */
Thomas Abrahamd23cb312016-04-23 22:18:13 +053013#define CONFIG_S5P
14
15#include <asm/arch/cpu.h> /* get chip and board defs */
16#include <linux/sizes.h>
17
Thomas Abrahamd23cb312016-04-23 22:18:13 +053018/* Miscellaneous configurable options */
19#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
20#define CONFIG_SYS_PBSIZE 1024 /* Print Buffer Size */
Thomas Abrahamd23cb312016-04-23 22:18:13 +053021
22/* Boot Argument Buffer Size */
23#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
24
25/* select serial console configuration */
Thomas Abrahamd23cb312016-04-23 22:18:13 +053026
Thomas Abrahamd23cb312016-04-23 22:18:13 +053027/* Timer input clock frequency */
28#define COUNTER_FREQUENCY 24000000
29
30/* Device Tree */
31#define CONFIG_DEVICE_TREE_LIST "exynos7420-espresso7420"
32
33/* IRAM Layout */
34#define CONFIG_IRAM_BASE 0x02100000
35#define CONFIG_IRAM_SIZE 0x58000
36#define CONFIG_IRAM_END (CONFIG_IRAM_BASE + CONFIG_IRAM_SIZE)
Thomas Abrahamf1855fc2016-11-16 18:49:16 +053037#define CPU_RELEASE_ADDR secondary_boot_addr
Thomas Abrahamd23cb312016-04-23 22:18:13 +053038
Thomas Abrahamd23cb312016-04-23 22:18:13 +053039/* select serial console configuration */
Thomas Abrahamd23cb312016-04-23 22:18:13 +053040
Thomas Abrahamd23cb312016-04-23 22:18:13 +053041#define PHYS_SDRAM_1 CONFIG_SYS_SDRAM_BASE
42#define PHYS_SDRAM_1_SIZE SDRAM_BANK_SIZE
43#define PHYS_SDRAM_2 (CONFIG_SYS_SDRAM_BASE + SDRAM_BANK_SIZE)
44#define PHYS_SDRAM_2_SIZE SDRAM_BANK_SIZE
45#define PHYS_SDRAM_3 (CONFIG_SYS_SDRAM_BASE + (2 * SDRAM_BANK_SIZE))
46#define PHYS_SDRAM_3_SIZE SDRAM_BANK_SIZE
47#define PHYS_SDRAM_4 (CONFIG_SYS_SDRAM_BASE + (3 * SDRAM_BANK_SIZE))
48#define PHYS_SDRAM_4_SIZE SDRAM_BANK_SIZE
49#define PHYS_SDRAM_5 (CONFIG_SYS_SDRAM_BASE + (4 * SDRAM_BANK_SIZE))
50#define PHYS_SDRAM_5_SIZE SDRAM_BANK_SIZE
51#define PHYS_SDRAM_6 (CONFIG_SYS_SDRAM_BASE + (5 * SDRAM_BANK_SIZE))
52#define PHYS_SDRAM_6_SIZE SDRAM_BANK_SIZE
53#define PHYS_SDRAM_7 (CONFIG_SYS_SDRAM_BASE + (6 * SDRAM_BANK_SIZE))
54#define PHYS_SDRAM_7_SIZE SDRAM_BANK_SIZE
55#define PHYS_SDRAM_8 (CONFIG_SYS_SDRAM_BASE + (7 * SDRAM_BANK_SIZE))
56#define PHYS_SDRAM_8_SIZE SDRAM_BANK_SIZE
57
58/* Configuration of ENV Blocks */
Thomas Abrahamd23cb312016-04-23 22:18:13 +053059
60#define BOOT_TARGET_DEVICES(func) \
61 func(MMC, mmc, 1) \
62 func(MMC, mmc, 0) \
63
64#ifndef MEM_LAYOUT_ENV_SETTINGS
65#define MEM_LAYOUT_ENV_SETTINGS \
66 "bootm_size=0x10000000\0" \
67 "kernel_addr_r=0x42000000\0" \
68 "fdt_addr_r=0x43000000\0" \
69 "ramdisk_addr_r=0x43300000\0" \
70 "scriptaddr=0x50000000\0" \
71 "pxefile_addr_r=0x51000000\0"
72#endif
73
74#ifndef EXYNOS_DEVICE_SETTINGS
75#define EXYNOS_DEVICE_SETTINGS \
76 "stdin=serial\0" \
77 "stdout=serial\0" \
78 "stderr=serial\0"
79#endif
80
81#ifndef EXYNOS_FDTFILE_SETTING
82#define EXYNOS_FDTFILE_SETTING
83#endif
84
85#define CONFIG_EXTRA_ENV_SETTINGS \
86 EXYNOS_DEVICE_SETTINGS \
87 EXYNOS_FDTFILE_SETTING \
88 MEM_LAYOUT_ENV_SETTINGS
89
90#endif /* __CONFIG_EXYNOS7420_COMMON_H */