Tom Rini | 10e4779 | 2018-05-06 17:58:06 -0400 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0+ */ |
Marek Vasut | ae723e1 | 2012-08-26 15:19:06 +0000 | [diff] [blame] | 2 | /* |
| 3 | * Generic bounce buffer implementation |
| 4 | * |
| 5 | * Copyright (C) 2012 Marek Vasut <marex@denx.de> |
Marek Vasut | ae723e1 | 2012-08-26 15:19:06 +0000 | [diff] [blame] | 6 | */ |
| 7 | |
| 8 | #ifndef __INCLUDE_BOUNCEBUF_H__ |
| 9 | #define __INCLUDE_BOUNCEBUF_H__ |
| 10 | |
Stephen Warren | 4a8629e | 2012-11-06 11:27:29 +0000 | [diff] [blame] | 11 | #include <linux/types.h> |
| 12 | |
Marek Vasut | ae723e1 | 2012-08-26 15:19:06 +0000 | [diff] [blame] | 13 | /* |
| 14 | * GEN_BB_READ -- Data are read from the buffer eg. by DMA hardware. |
| 15 | * The source buffer is copied into the bounce buffer (if unaligned, otherwise |
| 16 | * the source buffer is used directly) upon start() call, then the operation |
| 17 | * requiring the aligned transfer happens, then the bounce buffer is lost upon |
| 18 | * stop() call. |
| 19 | */ |
| 20 | #define GEN_BB_READ (1 << 0) |
| 21 | /* |
| 22 | * GEN_BB_WRITE -- Data are written into the buffer eg. by DMA hardware. |
| 23 | * The source buffer starts in an undefined state upon start() call, then the |
| 24 | * operation requiring the aligned transfer happens, then the bounce buffer is |
| 25 | * copied into the destination buffer (if unaligned, otherwise destination |
| 26 | * buffer is used directly) upon stop() call. |
| 27 | */ |
| 28 | #define GEN_BB_WRITE (1 << 1) |
| 29 | /* |
| 30 | * GEN_BB_RW -- Data are read and written into the buffer eg. by DMA hardware. |
| 31 | * The source buffer is copied into the bounce buffer (if unaligned, otherwise |
| 32 | * the source buffer is used directly) upon start() call, then the operation |
| 33 | * requiring the aligned transfer happens, then the bounce buffer is copied |
| 34 | * into the destination buffer (if unaligned, otherwise destination buffer is |
| 35 | * used directly) upon stop() call. |
| 36 | */ |
| 37 | #define GEN_BB_RW (GEN_BB_READ | GEN_BB_WRITE) |
| 38 | |
Stephen Warren | 4a8629e | 2012-11-06 11:27:29 +0000 | [diff] [blame] | 39 | struct bounce_buffer { |
| 40 | /* Copy of data parameter passed to start() */ |
| 41 | void *user_buffer; |
| 42 | /* |
| 43 | * DMA-aligned buffer. This field is always set to the value that |
| 44 | * should be used for DMA; either equal to .user_buffer, or to a |
| 45 | * freshly allocated aligned buffer. |
| 46 | */ |
| 47 | void *bounce_buffer; |
| 48 | /* Copy of len parameter passed to start() */ |
| 49 | size_t len; |
| 50 | /* DMA-aligned buffer length */ |
| 51 | size_t len_aligned; |
| 52 | /* Copy of flags parameter passed to start() */ |
| 53 | unsigned int flags; |
| 54 | }; |
| 55 | |
Marek Vasut | ae723e1 | 2012-08-26 15:19:06 +0000 | [diff] [blame] | 56 | /** |
| 57 | * bounce_buffer_start() -- Start the bounce buffer session |
Stephen Warren | 4a8629e | 2012-11-06 11:27:29 +0000 | [diff] [blame] | 58 | * state: stores state passed between bounce_buffer_{start,stop} |
Marek Vasut | ae723e1 | 2012-08-26 15:19:06 +0000 | [diff] [blame] | 59 | * data: pointer to buffer to be aligned |
| 60 | * len: length of the buffer |
Marek Vasut | ae723e1 | 2012-08-26 15:19:06 +0000 | [diff] [blame] | 61 | * flags: flags describing the transaction, see above. |
| 62 | */ |
Stephen Warren | 4a8629e | 2012-11-06 11:27:29 +0000 | [diff] [blame] | 63 | int bounce_buffer_start(struct bounce_buffer *state, void *data, |
| 64 | size_t len, unsigned int flags); |
Marek Vasut | ae723e1 | 2012-08-26 15:19:06 +0000 | [diff] [blame] | 65 | /** |
| 66 | * bounce_buffer_stop() -- Finish the bounce buffer session |
Stephen Warren | 4a8629e | 2012-11-06 11:27:29 +0000 | [diff] [blame] | 67 | * state: stores state passed between bounce_buffer_{start,stop} |
Marek Vasut | ae723e1 | 2012-08-26 15:19:06 +0000 | [diff] [blame] | 68 | */ |
Stephen Warren | 4a8629e | 2012-11-06 11:27:29 +0000 | [diff] [blame] | 69 | int bounce_buffer_stop(struct bounce_buffer *state); |
Marek Vasut | ae723e1 | 2012-08-26 15:19:06 +0000 | [diff] [blame] | 70 | |
| 71 | #endif |