blob: 96ff254f981254900123b9117471646da6931997 [file] [log] [blame]
Cyril Chemparathy464adc82012-07-24 12:22:16 +00001/*
2 * CPSW Ethernet Switch Driver
3 *
4 * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License as
8 * published by the Free Software Foundation version 2.
9 *
10 * This program is distributed "as is" WITHOUT ANY WARRANTY of any
11 * kind, whether express or implied; without even the implied warranty
12 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 */
15
16#ifndef _CPSW_H_
17#define _CPSW_H_
18
Faiz Abbas27866262019-03-18 13:54:37 +053019/* reg offset */
20#define CPSW_HOST_PORT_OFFSET 0x108
21#define CPSW_SLAVE0_OFFSET 0x208
22#define CPSW_SLAVE1_OFFSET 0x308
23#define CPSW_SLAVE_SIZE 0x100
24#define CPSW_CPDMA_OFFSET 0x800
25#define CPSW_HW_STATS 0x900
26#define CPSW_STATERAM_OFFSET 0xa00
27#define CPSW_CPTS_OFFSET 0xc00
28#define CPSW_ALE_OFFSET 0xd00
29#define CPSW_SLIVER0_OFFSET 0xd80
30#define CPSW_SLIVER1_OFFSET 0xdc0
31#define CPSW_BD_OFFSET 0x2000
32#define CPSW_MDIO_DIV 0xff
33
34#define AM335X_GMII_SEL_OFFSET 0x630
35
Cyril Chemparathy464adc82012-07-24 12:22:16 +000036struct cpsw_slave_data {
37 u32 slave_reg_ofs;
38 u32 sliver_reg_ofs;
Mugunthan V N4944f372014-02-18 07:31:52 -050039 int phy_addr;
Cyril Chemparathy464adc82012-07-24 12:22:16 +000040 int phy_if;
Dan Murphy4b7b24e2016-05-02 15:45:56 -050041 int phy_of_handle;
Cyril Chemparathy464adc82012-07-24 12:22:16 +000042};
43
44enum {
45 CPSW_CTRL_VERSION_1 = 0,
46 CPSW_CTRL_VERSION_2 /* am33xx like devices */
47};
48
49struct cpsw_platform_data {
50 u32 mdio_base;
51 u32 cpsw_base;
Mugunthan V N7ae228c2015-09-07 14:22:21 +053052 u32 mac_id;
53 u32 gmii_sel;
Cyril Chemparathy464adc82012-07-24 12:22:16 +000054 int mdio_div;
55 int channels; /* number of cpdma channels (symmetric) */
56 u32 cpdma_reg_ofs; /* cpdma register offset */
57 int slaves; /* number of slave cpgmac ports */
58 u32 ale_reg_ofs; /* address lookup engine reg offset */
59 int ale_entries; /* ale table size */
60 u32 host_port_reg_ofs; /* cpdma host port registers */
61 u32 hw_stats_reg_ofs; /* cpsw hw stats counters */
Mugunthan V Nff559872013-07-08 16:04:37 +053062 u32 bd_ram_ofs; /* Buffer Descriptor RAM offset */
Cyril Chemparathy464adc82012-07-24 12:22:16 +000063 u32 mac_control;
64 struct cpsw_slave_data *slave_data;
65 void (*control)(int enabled);
66 u32 host_port_num;
Mugunthan V N33e073e2014-05-22 14:37:10 +053067 u32 active_slave;
Mugunthan V N4d5fdb62016-10-13 19:33:38 +053068 bool rmii_clock_external;
Cyril Chemparathy464adc82012-07-24 12:22:16 +000069 u8 version;
Faiz Abbas5b5dc0f2019-03-18 13:54:32 +053070 const char *phy_sel_compat;
Faiz Abbas8ecdffe2019-03-18 13:54:34 +053071 u32 syscon_addr;
72 const char *macid_sel_compat;
Cyril Chemparathy464adc82012-07-24 12:22:16 +000073};
74
75int cpsw_register(struct cpsw_platform_data *data);
Faiz Abbas8ecdffe2019-03-18 13:54:34 +053076int ti_cm_get_macid_addr(struct udevice *dev, int slave,
77 struct cpsw_platform_data *data);
78void ti_cm_get_macid(struct udevice *dev, struct cpsw_platform_data *data,
79 u8 *mac_addr);
Sekhar Noricfc5cc82018-08-23 17:11:29 +053080int cpsw_get_slave_phy_addr(struct udevice *dev, int slave);
Cyril Chemparathy464adc82012-07-24 12:22:16 +000081
82#endif /* _CPSW_H_ */