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git01.mediatek.com / filogic / uboot / f3a4595c533d59890ebe3d4cee4e49b10b4b9f1c / . / include / configs / ti_omap5_common.h
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Tom Rini10e47792018-05-06 17:58:06 -0400[diff] [blame]1/* SPDX-License-Identifier: GPL-2.0+ */
Lokesh Vutla3e716e22013-02-17 23:34:35 +0000[diff] [blame]2/*
3 * (C) Copyright 2013
4 * Texas Instruments Incorporated.
5 * Sricharan R <r.sricharan@ti.com>
6 *
7 * Derived from OMAP4 done by:
8 * Aneesh V <aneesh@ti.com>
9 *
10 * TI OMAP5 AND DRA7XX common configuration settings
11 *
Tom Rinib3277f52013-08-09 11:22:18 -0400[diff] [blame]12 * For more details, please see the technical documents listed at
13 * http://www.ti.com/product/omap5432
Lokesh Vutla3e716e22013-02-17 23:34:35 +0000[diff] [blame]14 */
15
Enric Balletbò i Serra2785bb72013-12-06 21:30:19 +0100[diff] [blame]16#ifndef __CONFIG_TI_OMAP5_COMMON_H
17#define __CONFIG_TI_OMAP5_COMMON_H
Lokesh Vutla3e716e22013-02-17 23:34:35 +0000[diff] [blame]18
Tom Rinib3277f52013-08-09 11:22:18 -0400[diff] [blame]19/* Use General purpose timer 1 */
20#define CONFIG_SYS_TIMERBASE GPT2_BASE
Lokesh Vutla3e716e22013-02-17 23:34:35 +0000[diff] [blame]21
Tom Rini21089602013-08-20 08:53:52 -0400[diff] [blame]22/*
23 * For the DDR timing information we can either dynamically determine
24 * the timings to use or use pre-determined timings (based on using the
25 * dynamic method. Default to the static timing infomation.
26 */
Tom Rinib3277f52013-08-09 11:22:18 -0400[diff] [blame]27#define CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS
Tom Rinib3277f52013-08-09 11:22:18 -0400[diff] [blame]28#ifndef CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS
29#define CONFIG_SYS_AUTOMATIC_SDRAM_DETECTION
30#define CONFIG_SYS_DEFAULT_LPDDR2_TIMINGS
31#endif
32
Tom Rinib3277f52013-08-09 11:22:18 -0400[diff] [blame]33#define CONFIG_PALMAS_POWER
Tom Rinib3277f52013-08-09 11:22:18 -0400[diff] [blame]34
35#include <asm/arch/cpu.h>
36#include <asm/arch/omap.h>
37
Nishanth Menonad63dd72015-07-22 18:05:41 -0500[diff] [blame]38#include <configs/ti_armv7_omap.h>
Lokesh Vutla3e716e22013-02-17 23:34:35 +0000[diff] [blame]39
40/*
Tom Rinib3277f52013-08-09 11:22:18 -0400[diff] [blame]41 * Hardware drivers
Lokesh Vutla3e716e22013-02-17 23:34:35 +0000[diff] [blame]42 */
Thomas Chou52ac4432015-11-19 21:48:12 +0800[diff] [blame]43#define CONFIG_SYS_NS16550_CLK 48000000
Lokesh Vutla7ee789d2017-02-10 20:37:20 +0530[diff] [blame]44#if !defined(CONFIG_DM_SERIAL)
Lokesh Vutla3e716e22013-02-17 23:34:35 +0000[diff] [blame]45#define CONFIG_SYS_NS16550_SERIAL
46#define CONFIG_SYS_NS16550_REG_SIZE (-4)
Tom Rini2accd962015-09-17 16:47:04 -0400[diff] [blame]47#endif
Lokesh Vutla3e716e22013-02-17 23:34:35 +0000[diff] [blame]48
Lokesh Vutla3e716e22013-02-17 23:34:35 +0000[diff] [blame]49/*
50 * Environment setup
51 */
Tom Rini546c6c12013-04-05 06:21:45 +0000[diff] [blame]52
Kishon Vijay Abraham I24080762015-02-23 18:40:20 +0530[diff] [blame]53#ifndef DFUARGS
54#define DFUARGS
55#endif
56
Semen Protsenko334f5bb2017-06-14 21:34:23 +0300[diff] [blame]57#include <environment/ti/boot.h>
Sekhar Nori0ea56fe2017-04-06 14:52:56 +0530[diff] [blame]58#include <environment/ti/mmc.h>
Faiz Abbas1c2f44d2019-02-27 13:29:38 +0530[diff] [blame]59#include <environment/ti/nand.h>
Sekhar Nori0ea56fe2017-04-06 14:52:56 +0530[diff] [blame]60
Lokesh Vutla3e716e22013-02-17 23:34:35 +0000[diff] [blame]61#define CONFIG_EXTRA_ENV_SETTINGS \
Tom Rini96886f22014-03-28 15:03:29 -0400[diff] [blame]62 DEFAULT_LINUX_BOOT_ENV \
Lokesh Vutlab207c472015-08-28 13:35:07 +0530[diff] [blame]63 DEFAULT_MMC_TI_ARGS \
Lokesh Vutlac2913ac2016-11-29 11:58:00 +0530[diff] [blame]64 DEFAULT_FIT_TI_ARGS \
Semen Protsenko334f5bb2017-06-14 21:34:23 +0300[diff] [blame]65 DEFAULT_COMMON_BOOT_TI_ARGS \
66 DEFAULT_FDT_TI_ARGS \
Kishon Vijay Abraham I24080762015-02-23 18:40:20 +0530[diff] [blame]67 DFUARGS \
Cooper Jr., Franklin07610ab2015-04-21 07:51:04 -0500[diff] [blame]68 NETARGS \
Faiz Abbas1c2f44d2019-02-27 13:29:38 +0530[diff] [blame]69 NANDARGS \
Lokesh Vutla3e716e22013-02-17 23:34:35 +0000[diff] [blame]70
Tom Rini21089602013-08-20 08:53:52 -0400[diff] [blame]71/*
72 * SPL related defines. The Public RAM memory map the ROM defines the
Daniel Allred36d08242016-05-19 19:10:50 -0500[diff] [blame]73 * area between 0x40300000 and 0x4031E000 as a download area for OMAP5.
74 * On DRA7xx/AM57XX the download area is between 0x40300000 and 0x4037E000.
75 * We set CONFIG_SPL_DISPLAY_PRINT to have omap_rev_string() called and
Tom Rini21089602013-08-20 08:53:52 -0400[diff] [blame]76 * print some information.
77 */
Daniel Allred36d08242016-05-19 19:10:50 -0500[diff] [blame]78#ifdef CONFIG_TI_SECURE_DEVICE
79/*
80 * For memory booting on HS parts, the first 4KB of the internal RAM is
81 * reserved for secure world use and the flash loader image is
82 * preceded by a secure certificate. The SPL will therefore run in internal
83 * RAM from address 0x40301350 (0x40300000+0x1000(reserved)+0x350(cert)).
84 */
85#define TI_OMAP5_SECURE_BOOT_RESV_SRAM_SZ 0x1000
Andrew F. Davis0a371582019-01-17 13:43:05 -0600[diff] [blame]86#define CONFIG_SPL_TEXT_BASE CONFIG_ISW_ENTRY_ADDR
Daniel Allred420ffad2016-09-02 00:40:23 -0500[diff] [blame]87/* If no specific start address is specified then the secure EMIF
88 * region will be placed at the end of the DDR space. In order to prevent
89 * the main u-boot relocation from clobbering that memory and causing a
90 * firewall violation, we tell u-boot that memory is protected RAM (PRAM)
91 */
92#if (CONFIG_TI_SECURE_EMIF_REGION_START == 0)
93#define CONFIG_PRAM (CONFIG_TI_SECURE_EMIF_TOTAL_REGION_SIZE) >> 10
94#endif
Daniel Allred36d08242016-05-19 19:10:50 -0500[diff] [blame]95#else
96/*
97 * For all booting on GP parts, the flash loader image is
98 * downloaded into internal RAM at address 0x40300000.
99 */
100#define CONFIG_SPL_TEXT_BASE 0x40300000
101#endif
102
Tom Rinid9f808d2014-04-03 07:52:53 -0400[diff] [blame]103#define CONFIG_SYS_SPL_ARGS_ADDR (CONFIG_SYS_SDRAM_BASE + \
104 (128 << 20))
Mugunthan V Nd0320152015-09-29 14:42:26 +0530[diff] [blame]105#ifdef CONFIG_SPL_BUILD
Mugunthan V N6987f2d2015-12-24 16:08:18 +0530[diff] [blame]106#undef CONFIG_TIMER
Mugunthan V Nd0320152015-09-29 14:42:26 +0530[diff] [blame]107#endif
108
Enric Balletbò i Serra2785bb72013-12-06 21:30:19 +0100[diff] [blame]109#endif /* __CONFIG_TI_OMAP5_COMMON_H */