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Ricardo Ribalda Delgado78ea77e2008-10-21 18:29:46 +02001/*
2 * (C) Copyright 2008
Ricardo Ribalda Delgado5712d042016-01-26 11:24:08 +01003 * Ricado Ribalda-Universidad Autonoma de Madrid-ricardo.ribalda@gmail.com
Ricardo Ribalda Delgado78ea77e2008-10-21 18:29:46 +02004 * This work has been supported by: QTechnology http://qtec.com/
5 *
Wolfgang Denkd79de1d2013-07-08 09:37:19 +02006 * SPDX-License-Identifier: GPL-2.0+
Ricardo Ribalda Delgado78ea77e2008-10-21 18:29:46 +02007*/
8
9#include <config.h>
10#include <common.h>
11#include <asm/processor.h>
12
Ricardo Ribalda Delgado53b7e9f2016-01-26 11:24:20 +010013ulong get_PCI_freq(void)
Ricardo Ribalda Delgado78ea77e2008-10-21 18:29:46 +020014{
15 return 0;
16}
17
Ricardo Ribalda Delgado53b7e9f2016-01-26 11:24:20 +010018int checkboard(void)
Ricardo Ribalda Delgado78ea77e2008-10-21 18:29:46 +020019{
20 puts("Xilinx PPC405 Generic Board\n");
21 return 0;
22}
Ricardo Ribalda Delgado78ea77e2008-10-21 18:29:46 +020023
Ricardo Ribalda Delgado53b7e9f2016-01-26 11:24:20 +010024phys_size_t initdram(int board_type)
Ricardo Ribalda Delgado78ea77e2008-10-21 18:29:46 +020025{
26 return get_ram_size(XPAR_DDR2_SDRAM_MEM_BASEADDR,
27 CONFIG_SYS_SDRAM_SIZE_MB * 1024 * 1024);
28}
Ricardo Ribalda Delgado78ea77e2008-10-21 18:29:46 +020029
Ricardo Ribalda Delgado53b7e9f2016-01-26 11:24:20 +010030void get_sys_info(sys_info_t *sys_info)
Ricardo Ribalda Delgado78ea77e2008-10-21 18:29:46 +020031{
Ricardo Ribalda Delgado53b7e9f2016-01-26 11:24:20 +010032 sys_info->freqProcessor = XPAR_CORE_CLOCK_FREQ_HZ;
33 sys_info->freqPLB = XPAR_PLB_CLOCK_FREQ_HZ;
34 sys_info->freqPCI = 0;
Ricardo Ribalda Delgado78ea77e2008-10-21 18:29:46 +020035
36 return;
37}
Ricardo Ribalda Delgado4f40e132016-01-26 11:24:19 +010038
39int get_serial_clock(void){
40 return XPAR_UARTNS550_0_CLOCK_FREQ_HZ;
41}