| Masahiro Yamada | 8204bd1 | 2015-03-16 16:43:24 +0900 | [diff] [blame] | 1 | if ARCH_ZYNQ |
| Masahiro Yamada | a3cd898 | 2014-08-31 07:10:55 +0900 | [diff] [blame] | 2 | |
| Tien Fong Chee | 6fd0a71 | 2019-01-23 14:20:03 +0800 | [diff] [blame] | 3 | config SPL_FS_FAT |
| Simon Glass | 6172e2e | 2016-09-12 23:18:38 -0600 | [diff] [blame] | 4 | default y |
| 5 | |
| Simon Glass | f2a8946 | 2016-09-12 23:18:41 -0600 | [diff] [blame] | 6 | config SPL_LIBCOMMON_SUPPORT |
| 7 | default y |
| 8 | |
| Simon Glass | f6de257 | 2016-09-12 23:18:42 -0600 | [diff] [blame] | 9 | config SPL_LIBDISK_SUPPORT |
| 10 | default y |
| 11 | |
| Simon Glass | b16c92c | 2016-09-12 23:18:43 -0600 | [diff] [blame] | 12 | config SPL_LIBGENERIC_SUPPORT |
| 13 | default y |
| 14 | |
| Simon Glass | b58bfe0 | 2021-08-08 12:20:09 -0600 | [diff] [blame] | 15 | config SPL_MMC |
| Masahiro Yamada | 168c57d | 2017-01-30 19:46:51 +0900 | [diff] [blame] | 16 | default y if MMC_SDHCI_ZYNQ |
| Simon Glass | bd58f1d | 2016-09-12 23:18:44 -0600 | [diff] [blame] | 17 | |
| Simon Glass | f4d6039 | 2021-08-08 12:20:12 -0600 | [diff] [blame] | 18 | config SPL_SERIAL |
| Simon Glass | e076d6f | 2016-09-12 23:18:56 -0600 | [diff] [blame] | 19 | default y |
| 20 | |
| Simon Glass | 219d612 | 2016-09-12 23:18:57 -0600 | [diff] [blame] | 21 | config SPL_SPI_FLASH_SUPPORT |
| 22 | default y if ZYNQ_QSPI |
| 23 | |
| Simon Glass | a582047 | 2021-08-08 12:20:14 -0600 | [diff] [blame] | 24 | config SPL_SPI |
| Simon Glass | b24fdca | 2016-09-12 23:18:58 -0600 | [diff] [blame] | 25 | default y if ZYNQ_QSPI |
| 26 | |
| Siva Durga Prasad Paladugu | d8e4e1c | 2017-05-12 15:04:11 +0530 | [diff] [blame] | 27 | config ZYNQ_DDRC_INIT |
| 28 | bool "Zynq DDRC initialization" |
| 29 | default y |
| 30 | help |
| 31 | This option used to perform DDR specific initialization |
| 32 | if required. There might be cases like ddr less where we |
| 33 | want to skip ddr init and this option is useful for it. |
| 34 | |
| Masahiro Yamada | a3cd898 | 2014-08-31 07:10:55 +0900 | [diff] [blame] | 35 | config SYS_BOARD |
| Michal Simek | 1f5642a | 2018-03-04 16:15:15 +0100 | [diff] [blame] | 36 | string "Board name" |
| Masahiro Yamada | a3cd898 | 2014-08-31 07:10:55 +0900 | [diff] [blame] | 37 | default "zynq" |
| 38 | |
| 39 | config SYS_VENDOR |
| Mike Looijmans | 7d66606 | 2016-09-28 07:46:30 +0200 | [diff] [blame] | 40 | string "Vendor name" |
| Masahiro Yamada | a3cd898 | 2014-08-31 07:10:55 +0900 | [diff] [blame] | 41 | default "xilinx" |
| 42 | |
| 43 | config SYS_SOC |
| Masahiro Yamada | a3cd898 | 2014-08-31 07:10:55 +0900 | [diff] [blame] | 44 | default "zynq" |
| 45 | |
| Siva Durga Prasad Paladugu | 9adb526 | 2018-07-20 15:11:38 +0530 | [diff] [blame] | 46 | config SYS_MALLOC_LEN |
| 47 | default 0x1400000 |
| 48 | |
| Mike Looijmans | 96e706f | 2016-09-20 11:37:24 +0200 | [diff] [blame] | 49 | config BOOT_INIT_FILE |
| 50 | string "boot.bin init register filename" |
| 51 | default "" |
| 52 | help |
| 53 | Add register writes to boot.bin format (max 256 pairs). |
| 54 | Expect a table of register-value pairs, e.g. "0x12345678 0x4321" |
| 55 | |
| Vipul Kumar | 6254800 | 2018-02-28 15:53:28 +0530 | [diff] [blame] | 56 | config ZYNQ_SDHCI_MAX_FREQ |
| 57 | default 52000000 |
| 58 | |
| Michal Simek | 5f88485 | 2020-08-27 15:34:11 +0200 | [diff] [blame] | 59 | source "board/xilinx/Kconfig" |
| 60 | source "board/xilinx/zynq/Kconfig" |
| Bernhard Messerklinger | f37594c | 2025-04-04 09:28:00 +0200 | [diff] [blame^] | 61 | source "board/BuR/zynq/Kconfig" |
| Michal Simek | 5f88485 | 2020-08-27 15:34:11 +0200 | [diff] [blame] | 62 | |
| Masahiro Yamada | a3cd898 | 2014-08-31 07:10:55 +0900 | [diff] [blame] | 63 | endif |