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git01.mediatek.com / filogic / uboot / f36e9c7b8023f12718e7525829406bdc95c040ce / . / board / freescale / mx53loco / mx53loco.c
blob: 156f8b5a3aca81c070cac58baa7746d9d08d2526 [file] [log] [blame]
Jason Liuf5b81c82011-05-13 01:58:55 +0000[diff] [blame]1/*
2 * Copyright (C) 2011 Freescale Semiconductor, Inc.
3 * Jason Liu <r64343@freescale.com>
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
23
24#include <common.h>
25#include <asm/io.h>
26#include <asm/arch/imx-regs.h>
27#include <asm/arch/mx5x_pins.h>
28#include <asm/arch/sys_proto.h>
29#include <asm/arch/crm_regs.h>
30#include <asm/arch/iomux.h>
31#include <asm/arch/clock.h>
32#include <asm/errno.h>
33#include <netdev.h>
34#include <i2c.h>
35#include <mmc.h>
36#include <fsl_esdhc.h>
Stefano Babic831096b2011-08-21 10:59:33 +0200[diff] [blame]37#include <asm/gpio.h>
Jason Liuf5b81c82011-05-13 01:58:55 +0000[diff] [blame]38
39DECLARE_GLOBAL_DATA_PTR;
40
41u32 get_board_rev(void)
42{
43 return get_cpu_rev();
44}
45
46int dram_init(void)
47{
48 u32 size1, size2;
49
Albert ARIBAUDa9606732011-07-03 05:55:33 +0000[diff] [blame]50 size1 = get_ram_size((void *)PHYS_SDRAM_1, PHYS_SDRAM_1_SIZE);
51 size2 = get_ram_size((void *)PHYS_SDRAM_2, PHYS_SDRAM_2_SIZE);
Jason Liuf5b81c82011-05-13 01:58:55 +0000[diff] [blame]52
53 gd->ram_size = size1 + size2;
54
55 return 0;
56}
57void dram_init_banksize(void)
58{
59 gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
60 gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
61
62 gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
63 gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE;
64}
65
66static void setup_iomux_uart(void)
67{
68 /* UART1 RXD */
69 mxc_request_iomux(MX53_PIN_CSI0_D11, IOMUX_CONFIG_ALT2);
70 mxc_iomux_set_pad(MX53_PIN_CSI0_D11,
71 PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
72 PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
73 PAD_CTL_HYS_ENABLE | PAD_CTL_100K_PU |
74 PAD_CTL_ODE_OPENDRAIN_ENABLE);
75 mxc_iomux_set_input(MX53_UART1_IPP_UART_RXD_MUX_SELECT_INPUT, 0x1);
76
77 /* UART1 TXD */
78 mxc_request_iomux(MX53_PIN_CSI0_D10, IOMUX_CONFIG_ALT2);
79 mxc_iomux_set_pad(MX53_PIN_CSI0_D10,
80 PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
81 PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
82 PAD_CTL_HYS_ENABLE | PAD_CTL_100K_PU |
83 PAD_CTL_ODE_OPENDRAIN_ENABLE);
84}
85
86static void setup_iomux_fec(void)
87{
88 /*FEC_MDIO*/
89 mxc_request_iomux(MX53_PIN_FEC_MDIO, IOMUX_CONFIG_ALT0);
90 mxc_iomux_set_pad(MX53_PIN_FEC_MDIO,
91 PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
92 PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
93 PAD_CTL_22K_PU | PAD_CTL_ODE_OPENDRAIN_ENABLE);
94 mxc_iomux_set_input(MX53_FEC_FEC_MDI_SELECT_INPUT, 0x1);
95
96 /*FEC_MDC*/
97 mxc_request_iomux(MX53_PIN_FEC_MDC, IOMUX_CONFIG_ALT0);
98 mxc_iomux_set_pad(MX53_PIN_FEC_MDC, PAD_CTL_DRV_HIGH);
99
100 /* FEC RXD1 */
101 mxc_request_iomux(MX53_PIN_FEC_RXD1, IOMUX_CONFIG_ALT0);
102 mxc_iomux_set_pad(MX53_PIN_FEC_RXD1,
103 PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE);
104
105 /* FEC RXD0 */
106 mxc_request_iomux(MX53_PIN_FEC_RXD0, IOMUX_CONFIG_ALT0);
107 mxc_iomux_set_pad(MX53_PIN_FEC_RXD0,
108 PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE);
109
110 /* FEC TXD1 */
111 mxc_request_iomux(MX53_PIN_FEC_TXD1, IOMUX_CONFIG_ALT0);
112 mxc_iomux_set_pad(MX53_PIN_FEC_TXD1, PAD_CTL_DRV_HIGH);
113
114 /* FEC TXD0 */
115 mxc_request_iomux(MX53_PIN_FEC_TXD0, IOMUX_CONFIG_ALT0);
116 mxc_iomux_set_pad(MX53_PIN_FEC_TXD0, PAD_CTL_DRV_HIGH);
117
118 /* FEC TX_EN */
119 mxc_request_iomux(MX53_PIN_FEC_TX_EN, IOMUX_CONFIG_ALT0);
120 mxc_iomux_set_pad(MX53_PIN_FEC_TX_EN, PAD_CTL_DRV_HIGH);
121
122 /* FEC TX_CLK */
123 mxc_request_iomux(MX53_PIN_FEC_REF_CLK, IOMUX_CONFIG_ALT0);
124 mxc_iomux_set_pad(MX53_PIN_FEC_REF_CLK,
125 PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE);
126
127 /* FEC RX_ER */
128 mxc_request_iomux(MX53_PIN_FEC_RX_ER, IOMUX_CONFIG_ALT0);
129 mxc_iomux_set_pad(MX53_PIN_FEC_RX_ER,
130 PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE);
131
132 /* FEC CRS */
133 mxc_request_iomux(MX53_PIN_FEC_CRS_DV, IOMUX_CONFIG_ALT0);
134 mxc_iomux_set_pad(MX53_PIN_FEC_CRS_DV,
135 PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE);
136}
137
138#ifdef CONFIG_FSL_ESDHC
139struct fsl_esdhc_cfg esdhc_cfg[2] = {
140 {MMC_SDHC1_BASE_ADDR, 1},
141 {MMC_SDHC3_BASE_ADDR, 1},
142};
143
144int board_mmc_getcd(u8 *cd, struct mmc *mmc)
145{
146 struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
147
148 if (cfg->esdhc_base == MMC_SDHC1_BASE_ADDR)
Stefano Babic831096b2011-08-21 10:59:33 +0200[diff] [blame]149 *cd = gpio_get_value(77); /*GPIO3_13*/
Jason Liuf5b81c82011-05-13 01:58:55 +0000[diff] [blame]150 else
Stefano Babic831096b2011-08-21 10:59:33 +0200[diff] [blame]151 *cd = gpio_get_value(75); /*GPIO3_11*/
Jason Liuf5b81c82011-05-13 01:58:55 +0000[diff] [blame]152
153 return 0;
154}
155
156int board_mmc_init(bd_t *bis)
157{
158 u32 index;
159 s32 status = 0;
160
161 for (index = 0; index < CONFIG_SYS_FSL_ESDHC_NUM; index++) {
162 switch (index) {
163 case 0:
164 mxc_request_iomux(MX53_PIN_SD1_CMD, IOMUX_CONFIG_ALT0);
165 mxc_request_iomux(MX53_PIN_SD1_CLK, IOMUX_CONFIG_ALT0);
166 mxc_request_iomux(MX53_PIN_SD1_DATA0,
167 IOMUX_CONFIG_ALT0);
168 mxc_request_iomux(MX53_PIN_SD1_DATA1,
169 IOMUX_CONFIG_ALT0);
170 mxc_request_iomux(MX53_PIN_SD1_DATA2,
171 IOMUX_CONFIG_ALT0);
172 mxc_request_iomux(MX53_PIN_SD1_DATA3,
173 IOMUX_CONFIG_ALT0);
174 mxc_request_iomux(MX53_PIN_EIM_DA13,
175 IOMUX_CONFIG_ALT1);
176
177 mxc_iomux_set_pad(MX53_PIN_SD1_CMD,
178 PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
179 PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
180 PAD_CTL_HYS_ENABLE | PAD_CTL_100K_PU);
181 mxc_iomux_set_pad(MX53_PIN_SD1_CLK,
182 PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
183 PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU |
184 PAD_CTL_DRV_HIGH);
185 mxc_iomux_set_pad(MX53_PIN_SD1_DATA0,
186 PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
187 PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
188 PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU);
189 mxc_iomux_set_pad(MX53_PIN_SD1_DATA1,
190 PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
191 PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
192 PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU);
193 mxc_iomux_set_pad(MX53_PIN_SD1_DATA2,
194 PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
195 PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
196 PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU);
197 mxc_iomux_set_pad(MX53_PIN_SD1_DATA3,
198 PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
199 PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
200 PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU);
201 break;
202 case 1:
203 mxc_request_iomux(MX53_PIN_ATA_RESET_B,
204 IOMUX_CONFIG_ALT2);
205 mxc_request_iomux(MX53_PIN_ATA_IORDY,
206 IOMUX_CONFIG_ALT2);
207 mxc_request_iomux(MX53_PIN_ATA_DATA8,
208 IOMUX_CONFIG_ALT4);
209 mxc_request_iomux(MX53_PIN_ATA_DATA9,
210 IOMUX_CONFIG_ALT4);
211 mxc_request_iomux(MX53_PIN_ATA_DATA10,
212 IOMUX_CONFIG_ALT4);
213 mxc_request_iomux(MX53_PIN_ATA_DATA11,
214 IOMUX_CONFIG_ALT4);
215 mxc_request_iomux(MX53_PIN_ATA_DATA0,
216 IOMUX_CONFIG_ALT4);
217 mxc_request_iomux(MX53_PIN_ATA_DATA1,
218 IOMUX_CONFIG_ALT4);
219 mxc_request_iomux(MX53_PIN_ATA_DATA2,
220 IOMUX_CONFIG_ALT4);
221 mxc_request_iomux(MX53_PIN_ATA_DATA3,
222 IOMUX_CONFIG_ALT4);
223 mxc_request_iomux(MX53_PIN_EIM_DA11,
224 IOMUX_CONFIG_ALT1);
225
226 mxc_iomux_set_pad(MX53_PIN_ATA_RESET_B,
227 PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
228 PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
229 PAD_CTL_HYS_ENABLE | PAD_CTL_100K_PU);
230 mxc_iomux_set_pad(MX53_PIN_ATA_IORDY,
231 PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
232 PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU |
233 PAD_CTL_DRV_HIGH);
234 mxc_iomux_set_pad(MX53_PIN_ATA_DATA8,
235 PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
236 PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
237 PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU);
238 mxc_iomux_set_pad(MX53_PIN_ATA_DATA9,
239 PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
240 PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
241 PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU);
242 mxc_iomux_set_pad(MX53_PIN_ATA_DATA10,
243 PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
244 PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
245 PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU);
246 mxc_iomux_set_pad(MX53_PIN_ATA_DATA11,
247 PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
248 PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
249 PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU);
250 mxc_iomux_set_pad(MX53_PIN_ATA_DATA0,
251 PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
252 PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
253 PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU);
254 mxc_iomux_set_pad(MX53_PIN_ATA_DATA1,
255 PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
256 PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
257 PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU);
258 mxc_iomux_set_pad(MX53_PIN_ATA_DATA2,
259 PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
260 PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
261 PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU);
262 mxc_iomux_set_pad(MX53_PIN_ATA_DATA3,
263 PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
264 PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
265 PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU);
266
267 break;
268 default:
269 printf("Warning: you configured more ESDHC controller"
270 "(%d) as supported by the board(2)\n",
271 CONFIG_SYS_FSL_ESDHC_NUM);
272 return status;
273 }
274 status |= fsl_esdhc_initialize(bis, &esdhc_cfg[index]);
275 }
276
277 return status;
278}
279#endif
280
281int board_early_init_f(void)
282{
283 setup_iomux_uart();
284 setup_iomux_fec();
285
286 return 0;
287}
288
289int board_init(void)
290{
Jason Liuf5b81c82011-05-13 01:58:55 +0000[diff] [blame]291 gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
292
293 return 0;
294}
295
296int checkboard(void)
297{
298 puts("Board: MX53 LOCO\n");
299
300 return 0;
301}