Siva Durga Prasad Paladugu | 775aa95 | 2019-01-08 21:47:26 +0530 | [diff] [blame] | 1 | // SPDX-License-Identifier: GPL-2.0 |
| 2 | /* |
| 3 | * (C) Copyright 2019 Xilinx, Inc. |
| 4 | * Siva Durga Prasad <siva.durga.paladugu@xilinx.com> |
| 5 | */ |
| 6 | |
| 7 | #include <common.h> |
| 8 | #include <asm/io.h> |
| 9 | #include <asm/arch/hardware.h> |
| 10 | #include <asm/arch/sys_proto.h> |
| 11 | |
| 12 | DECLARE_GLOBAL_DATA_PTR; |
| 13 | |
| 14 | #define HALT 0 |
| 15 | #define RELEASE 1 |
| 16 | |
| 17 | #define VERSAL_RPU_CFG_CPU_HALT_MASK 0x01 |
| 18 | #define VERSAL_RPU_GLBL_CTRL_SPLIT_LOCK_MASK 0x08 |
| 19 | #define VERSAL_RPU_GLBL_CTRL_TCM_COMB_MASK 0x40 |
| 20 | #define VERSAL_RPU_GLBL_CTRL_SLCLAMP_MASK 0x10 |
| 21 | |
| 22 | #define VERSAL_CRLAPB_RST_LPD_AMBA_RST_MASK 0x04 |
| 23 | #define VERSAL_CRLAPB_RST_LPD_R50_RST_MASK 0x01 |
| 24 | #define VERSAL_CRLAPB_RST_LPD_R51_RST_MASK 0x02 |
| 25 | #define VERSAL_CRL_RST_CPU_R5_RESET_PGE_MASK 0x10 |
| 26 | #define VERSAL_CRLAPB_CPU_R5_CTRL_CLKACT_MASK 0x1000000 |
| 27 | |
| 28 | void set_r5_halt_mode(u8 halt, u8 mode) |
| 29 | { |
| 30 | u32 tmp; |
| 31 | |
| 32 | tmp = readl(&rpu_base->rpu0_cfg); |
| 33 | if (halt == HALT) |
| 34 | tmp &= ~VERSAL_RPU_CFG_CPU_HALT_MASK; |
| 35 | else |
| 36 | tmp |= VERSAL_RPU_CFG_CPU_HALT_MASK; |
| 37 | writel(tmp, &rpu_base->rpu0_cfg); |
| 38 | |
| 39 | if (mode == TCM_LOCK) { |
| 40 | tmp = readl(&rpu_base->rpu1_cfg); |
| 41 | if (halt == HALT) |
| 42 | tmp &= ~VERSAL_RPU_CFG_CPU_HALT_MASK; |
| 43 | else |
| 44 | tmp |= VERSAL_RPU_CFG_CPU_HALT_MASK; |
| 45 | writel(tmp, &rpu_base->rpu1_cfg); |
| 46 | } |
| 47 | } |
| 48 | |
| 49 | void set_r5_tcm_mode(u8 mode) |
| 50 | { |
| 51 | u32 tmp; |
| 52 | |
| 53 | tmp = readl(&rpu_base->rpu_glbl_ctrl); |
| 54 | if (mode == TCM_LOCK) { |
| 55 | tmp &= ~VERSAL_RPU_GLBL_CTRL_SPLIT_LOCK_MASK; |
| 56 | tmp |= VERSAL_RPU_GLBL_CTRL_TCM_COMB_MASK | |
| 57 | VERSAL_RPU_GLBL_CTRL_SLCLAMP_MASK; |
| 58 | } else { |
| 59 | tmp |= VERSAL_RPU_GLBL_CTRL_SPLIT_LOCK_MASK; |
| 60 | tmp &= ~(VERSAL_RPU_GLBL_CTRL_TCM_COMB_MASK | |
| 61 | VERSAL_RPU_GLBL_CTRL_SLCLAMP_MASK); |
| 62 | } |
| 63 | |
| 64 | writel(tmp, &rpu_base->rpu_glbl_ctrl); |
| 65 | } |
| 66 | |
| 67 | void release_r5_reset(u8 mode) |
| 68 | { |
| 69 | u32 tmp; |
| 70 | |
| 71 | tmp = readl(&crlapb_base->rst_cpu_r5); |
| 72 | tmp &= ~(VERSAL_CRLAPB_RST_LPD_AMBA_RST_MASK | |
| 73 | VERSAL_CRLAPB_RST_LPD_R50_RST_MASK | |
| 74 | VERSAL_CRL_RST_CPU_R5_RESET_PGE_MASK); |
| 75 | |
| 76 | if (mode == TCM_LOCK) |
| 77 | tmp &= ~VERSAL_CRLAPB_RST_LPD_R51_RST_MASK; |
| 78 | |
| 79 | writel(tmp, &crlapb_base->rst_cpu_r5); |
| 80 | } |
| 81 | |
| 82 | void enable_clock_r5(void) |
| 83 | { |
| 84 | u32 tmp; |
| 85 | |
| 86 | tmp = readl(&crlapb_base->cpu_r5_ctrl); |
| 87 | tmp |= VERSAL_CRLAPB_CPU_R5_CTRL_CLKACT_MASK; |
| 88 | writel(tmp, &crlapb_base->cpu_r5_ctrl); |
| 89 | } |
| 90 | |
| 91 | void initialize_tcm(bool mode) |
| 92 | { |
| 93 | if (!mode) { |
| 94 | set_r5_tcm_mode(TCM_LOCK); |
| 95 | set_r5_halt_mode(HALT, TCM_LOCK); |
| 96 | enable_clock_r5(); |
| 97 | release_r5_reset(TCM_LOCK); |
| 98 | } else { |
| 99 | set_r5_tcm_mode(TCM_SPLIT); |
| 100 | set_r5_halt_mode(HALT, TCM_SPLIT); |
| 101 | enable_clock_r5(); |
| 102 | release_r5_reset(TCM_SPLIT); |
| 103 | } |
| 104 | } |
| 105 | |
| 106 | void tcm_init(u8 mode) |
| 107 | { |
| 108 | puts("WARNING: Initializing TCM overwrites TCM content\n"); |
| 109 | initialize_tcm(mode); |
| 110 | memset((void *)VERSAL_TCM_BASE_ADDR, 0, VERSAL_TCM_SIZE); |
| 111 | } |