Tom Rini | 10e4779 | 2018-05-06 17:58:06 -0400 | [diff] [blame] | 1 | // SPDX-License-Identifier: GPL-2.0+ |
Hugo Villeneuve | 4e352ef | 2008-07-11 15:10:13 -0400 | [diff] [blame] | 2 | /* |
| 3 | * Power and Sleep Controller (PSC) functions. |
| 4 | * |
| 5 | * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net> |
| 6 | * Copyright (C) 2008 Lyrtech <www.lyrtech.com> |
| 7 | * Copyright (C) 2004 Texas Instruments. |
Hugo Villeneuve | 4e352ef | 2008-07-11 15:10:13 -0400 | [diff] [blame] | 8 | */ |
| 9 | |
| 10 | #include <common.h> |
| 11 | #include <asm/arch/hardware.h> |
Sekhar Nori | 302fc2f | 2009-11-12 11:07:22 -0500 | [diff] [blame] | 12 | #include <asm/io.h> |
Hugo Villeneuve | 4e352ef | 2008-07-11 15:10:13 -0400 | [diff] [blame] | 13 | |
| 14 | /* |
David Brownell | 5f02add | 2009-05-15 23:44:08 +0200 | [diff] [blame] | 15 | * The PSC manages three inputs to a "module" which may be a peripheral or |
| 16 | * CPU. Those inputs are the module's: clock; reset signal; and sometimes |
| 17 | * its power domain. For our purposes, we only care whether clock and power |
| 18 | * are active, and the module is out of reset. |
| 19 | * |
| 20 | * DaVinci chips may include two separate power domains: "Always On" and "DSP". |
| 21 | * Chips without a DSP generally have only one domain. |
| 22 | * |
| 23 | * The "Always On" power domain is always on when the chip is on, and is |
| 24 | * powered by the VDD pins (on DM644X). The majority of DaVinci modules |
| 25 | * lie within the "Always On" power domain. |
| 26 | * |
| 27 | * A separate domain called the "DSP" domain houses the C64x+ and other video |
| 28 | * hardware such as VICP. In some chips, the "DSP" domain is not always on. |
| 29 | * The "DSP" power domain is powered by the CVDDDSP pins (on DM644X). |
Hugo Villeneuve | 4e352ef | 2008-07-11 15:10:13 -0400 | [diff] [blame] | 30 | */ |
| 31 | |
| 32 | /* Works on Always On power domain only (no PD argument) */ |
Christian Riesch | a4cd16f | 2011-10-12 21:26:43 +0000 | [diff] [blame] | 33 | static void lpsc_transition(unsigned int id, unsigned int state) |
Hugo Villeneuve | 4e352ef | 2008-07-11 15:10:13 -0400 | [diff] [blame] | 34 | { |
Sekhar Nori | 302fc2f | 2009-11-12 11:07:22 -0500 | [diff] [blame] | 35 | dv_reg_p mdstat, mdctl, ptstat, ptcmd; |
Sekhar Nori | 302fc2f | 2009-11-12 11:07:22 -0500 | [diff] [blame] | 36 | struct davinci_psc_regs *psc_regs; |
Hugo Villeneuve | 4e352ef | 2008-07-11 15:10:13 -0400 | [diff] [blame] | 37 | |
Sekhar Nori | 302fc2f | 2009-11-12 11:07:22 -0500 | [diff] [blame] | 38 | if (id < DAVINCI_LPSC_PSC1_BASE) { |
| 39 | if (id >= PSC_PSC0_MODULE_ID_CNT) |
| 40 | return; |
| 41 | psc_regs = davinci_psc0_regs; |
| 42 | mdstat = &psc_regs->psc0.mdstat[id]; |
| 43 | mdctl = &psc_regs->psc0.mdctl[id]; |
| 44 | } else { |
| 45 | id -= DAVINCI_LPSC_PSC1_BASE; |
| 46 | if (id >= PSC_PSC1_MODULE_ID_CNT) |
| 47 | return; |
| 48 | psc_regs = davinci_psc1_regs; |
| 49 | mdstat = &psc_regs->psc1.mdstat[id]; |
| 50 | mdctl = &psc_regs->psc1.mdctl[id]; |
| 51 | } |
| 52 | ptstat = &psc_regs->ptstat; |
| 53 | ptcmd = &psc_regs->ptcmd; |
Hugo Villeneuve | 4e352ef | 2008-07-11 15:10:13 -0400 | [diff] [blame] | 54 | |
Sekhar Nori | 302fc2f | 2009-11-12 11:07:22 -0500 | [diff] [blame] | 55 | while (readl(ptstat) & 0x01) |
David Brownell | 5f02add | 2009-05-15 23:44:08 +0200 | [diff] [blame] | 56 | continue; |
Hugo Villeneuve | 4e352ef | 2008-07-11 15:10:13 -0400 | [diff] [blame] | 57 | |
Christian Riesch | a4cd16f | 2011-10-12 21:26:43 +0000 | [diff] [blame] | 58 | if ((readl(mdstat) & PSC_MDSTAT_STATE) == state) |
| 59 | return; /* Already in that state */ |
Hugo Villeneuve | 4e352ef | 2008-07-11 15:10:13 -0400 | [diff] [blame] | 60 | |
Christian Riesch | a4cd16f | 2011-10-12 21:26:43 +0000 | [diff] [blame] | 61 | writel((readl(mdctl) & ~PSC_MDCTL_NEXT) | state, mdctl); |
Sekhar Nori | 302fc2f | 2009-11-12 11:07:22 -0500 | [diff] [blame] | 62 | writel(0x01, ptcmd); |
Hugo Villeneuve | 4e352ef | 2008-07-11 15:10:13 -0400 | [diff] [blame] | 63 | |
Sekhar Nori | 302fc2f | 2009-11-12 11:07:22 -0500 | [diff] [blame] | 64 | while (readl(ptstat) & 0x01) |
David Brownell | 5f02add | 2009-05-15 23:44:08 +0200 | [diff] [blame] | 65 | continue; |
Christian Riesch | a4cd16f | 2011-10-12 21:26:43 +0000 | [diff] [blame] | 66 | while ((readl(mdstat) & PSC_MDSTAT_STATE) != state) |
David Brownell | 5f02add | 2009-05-15 23:44:08 +0200 | [diff] [blame] | 67 | continue; |
Hugo Villeneuve | 4e352ef | 2008-07-11 15:10:13 -0400 | [diff] [blame] | 68 | } |
| 69 | |
Christian Riesch | a4cd16f | 2011-10-12 21:26:43 +0000 | [diff] [blame] | 70 | void lpsc_on(unsigned int id) |
| 71 | { |
| 72 | lpsc_transition(id, 0x03); |
| 73 | } |
| 74 | |
| 75 | void lpsc_syncreset(unsigned int id) |
| 76 | { |
| 77 | lpsc_transition(id, 0x01); |
| 78 | } |
| 79 | |
Sughosh Ganu | 282e2af | 2012-08-09 10:45:20 +0000 | [diff] [blame] | 80 | void lpsc_disable(unsigned int id) |
| 81 | { |
| 82 | lpsc_transition(id, 0x0); |
| 83 | } |