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Tom Rini10e47792018-05-06 17:58:06 -04001/* SPDX-License-Identifier: GPL-2.0+ */
Fabio Estevama7b1dc92011-05-13 03:15:11 +00002/*
3 * Copyright (C) 2011 Freescale Semiconductor, Inc.
4 *
Fabio Estevam60a7ec22011-09-22 08:07:20 +00005 * Configuration settings for the MX53SMD Freescale board.
Fabio Estevama7b1dc92011-05-13 03:15:11 +00006 */
7
8#ifndef __CONFIG_H
9#define __CONFIG_H
10
Fabio Estevam60a7ec22011-09-22 08:07:20 +000011#define CONFIG_MACH_TYPE MACH_TYPE_MX53_SMD
12
Fabio Estevama7b1dc92011-05-13 03:15:11 +000013#include <asm/arch/imx-regs.h>
14
15#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */
Fabio Estevama7b1dc92011-05-13 03:15:11 +000016#define CONFIG_SETUP_MEMORY_TAGS
17#define CONFIG_INITRD_TAG
Fabio Estevam5db5f412013-04-24 14:44:26 +000018#define CONFIG_REVISION_TAG
Fabio Estevama7b1dc92011-05-13 03:15:11 +000019
Gong Qianyu52de2e52015-10-26 19:47:42 +080020#define CONFIG_SYS_FSL_CLK
Fabio Estevam0bd0e852014-04-22 15:34:57 -030021
Fabio Estevama7b1dc92011-05-13 03:15:11 +000022/* Size of malloc() pool */
23#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 2 * 1024 * 1024)
24
Stefano Babic1ca47d92011-11-22 15:22:39 +010025#define CONFIG_MXC_UART_BASE UART1_BASE
Fabio Estevama7b1dc92011-05-13 03:15:11 +000026
27/* I2C Configs */
trem03997412013-09-21 18:13:36 +020028#define CONFIG_SYS_I2C
29#define CONFIG_SYS_I2C_MXC
Albert ARIBAUD \\(3ADEV\\)eb943872015-09-21 22:43:38 +020030#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */
31#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */
York Sunf1a52162015-03-20 10:20:40 -070032#define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */
Fabio Estevama7b1dc92011-05-13 03:15:11 +000033
34/* MMC Configs */
Fabio Estevama7b1dc92011-05-13 03:15:11 +000035#define CONFIG_SYS_FSL_ESDHC_ADDR 0
36#define CONFIG_SYS_FSL_ESDHC_NUM 1
37
Fabio Estevama7b1dc92011-05-13 03:15:11 +000038/* Eth Configs */
39#define CONFIG_HAS_ETH1
Fabio Estevama7b1dc92011-05-13 03:15:11 +000040
41#define CONFIG_FEC_MXC
42#define IMX_FEC_BASE FEC_BASE_ADDR
43#define CONFIG_FEC_MXC_PHYADDR 0x1F
44
Fabio Estevama7b1dc92011-05-13 03:15:11 +000045/* Command definition */
Fabio Estevama7b1dc92011-05-13 03:15:11 +000046
Wolfgang Grandegger96529e22011-10-17 08:21:56 +000047#define CONFIG_ETHPRIME "FEC0"
Fabio Estevama7b1dc92011-05-13 03:15:11 +000048
49#define CONFIG_LOADADDR 0x70800000 /* loadaddr env var */
Fabio Estevama7b1dc92011-05-13 03:15:11 +000050
51#define CONFIG_EXTRA_ENV_SETTINGS \
52 "script=boot.scr\0" \
53 "uimage=uImage\0" \
54 "mmcdev=0\0" \
55 "mmcpart=2\0" \
56 "mmcroot=/dev/mmcblk0p3 rw\0" \
57 "mmcrootfstype=ext3 rootwait\0" \
58 "mmcargs=setenv bootargs console=ttymxc0,${baudrate} " \
59 "root=${mmcroot} " \
60 "rootfstype=${mmcrootfstype}\0" \
61 "loadbootscript=" \
62 "fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \
63 "bootscript=echo Running bootscript from mmc ...; " \
64 "source\0" \
65 "loaduimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${uimage}\0" \
66 "mmcboot=echo Booting from mmc ...; " \
67 "run mmcargs; " \
68 "bootm\0" \
69 "netargs=setenv bootargs console=ttymxc0,${baudrate} " \
70 "root=/dev/nfs " \
71 "ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \
72 "netboot=echo Booting from net ...; " \
73 "run netargs; " \
74 "dhcp ${uimage}; bootm\0" \
75
76#define CONFIG_BOOTCOMMAND \
Andrew Bradforde1c7c8a2012-10-01 05:06:52 +000077 "mmc dev ${mmcdev}; if mmc rescan; then " \
Fabio Estevama7b1dc92011-05-13 03:15:11 +000078 "if run loadbootscript; then " \
79 "run bootscript; " \
80 "else " \
81 "if run loaduimage; then " \
82 "run mmcboot; " \
83 "else run netboot; " \
84 "fi; " \
85 "fi; " \
86 "else run netboot; fi"
87#define CONFIG_ARP_TIMEOUT 200UL
88
89/* Miscellaneous configurable options */
Fabio Estevama7b1dc92011-05-13 03:15:11 +000090
Fabio Estevama7b1dc92011-05-13 03:15:11 +000091#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
92
Fabio Estevama7b1dc92011-05-13 03:15:11 +000093/* Physical Memory Map */
Fabio Estevama7b1dc92011-05-13 03:15:11 +000094#define PHYS_SDRAM_1 CSD0_BASE_ADDR
95#define PHYS_SDRAM_1_SIZE (512 * 1024 * 1024)
96#define PHYS_SDRAM_2 CSD1_BASE_ADDR
97#define PHYS_SDRAM_2_SIZE (512 * 1024 * 1024)
98#define PHYS_SDRAM_SIZE (PHYS_SDRAM_1_SIZE + PHYS_SDRAM_2_SIZE)
99
100#define CONFIG_SYS_SDRAM_BASE (PHYS_SDRAM_1)
101#define CONFIG_SYS_INIT_RAM_ADDR (IRAM_BASE_ADDR)
102#define CONFIG_SYS_INIT_RAM_SIZE (IRAM_SIZE)
103
104#define CONFIG_SYS_INIT_SP_OFFSET \
105 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
106#define CONFIG_SYS_INIT_SP_ADDR \
107 (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
108
Masahiro Yamada8cea9b52017-02-11 22:43:54 +0900109/* environment organization */
Fabio Estevama7b1dc92011-05-13 03:15:11 +0000110
Fabio Estevama7b1dc92011-05-13 03:15:11 +0000111#endif /* __CONFIG_H */