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Tom Rini10e47792018-05-06 17:58:06 -04001/* SPDX-License-Identifier: GPL-2.0+ */
Stefano Babic1f76ac12011-11-30 23:56:52 +00002/*
3 * Copyright (C) 2011
4 * Stefano Babic, DENX Software Engineering, sbabic@denx.de.
5 *
6 * Copyright (C) 2009 TechNexion Ltd.
Stefano Babic1f76ac12011-11-30 23:56:52 +00007 */
8
9#ifndef __TAM3517_H
10#define __TAM3517_H
11
12/*
13 * High Level Configuration Options
14 */
Stefano Babic1f76ac12011-11-30 23:56:52 +000015
Stefano Babic1f76ac12011-11-30 23:56:52 +000016#include <asm/arch/cpu.h> /* get chip and board defs */
Nishanth Menonfa96c962015-03-09 17:12:04 -050017#include <asm/arch/omap.h>
Stefano Babic1f76ac12011-11-30 23:56:52 +000018
Stefano Babic1f76ac12011-11-30 23:56:52 +000019/* Clock Defines */
20#define V_OSCK 26000000 /* Clock output from T2 */
21#define V_SCLK (V_OSCK >> 1)
22
Stefano Babic1f76ac12011-11-30 23:56:52 +000023#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */
24#define CONFIG_SETUP_MEMORY_TAGS
25#define CONFIG_INITRD_TAG
26#define CONFIG_REVISION_TAG
27
28/*
Stefano Babic1f76ac12011-11-30 23:56:52 +000029 * DDR related
30 */
Stefano Babic1f76ac12011-11-30 23:56:52 +000031#define CONFIG_SYS_CS0_SIZE (256 * 1024 * 1024)
32
33/*
34 * Hardware drivers
35 */
36
37/*
38 * NS16550 Configuration
39 */
Stefano Babic1f76ac12011-11-30 23:56:52 +000040#define CONFIG_SYS_NS16550_SERIAL
41#define CONFIG_SYS_NS16550_REG_SIZE (-4)
42#define CONFIG_SYS_NS16550_CLK 48000000 /* 48MHz (APLL96/2) */
43
44/*
45 * select serial console configuration
46 */
Stefano Babic1f76ac12011-11-30 23:56:52 +000047#define CONFIG_SYS_NS16550_COM1 OMAP34XX_UART1
Stefano Babic1f76ac12011-11-30 23:56:52 +000048
Stefano Babic1f76ac12011-11-30 23:56:52 +000049#define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600,\
50 115200}
Stefano Babic1f76ac12011-11-30 23:56:52 +000051/* EHCI */
Stefano Babic1f76ac12011-11-30 23:56:52 +000052#define CONFIG_OMAP_EHCI_PHY1_RESET_GPIO 25
Stefano Babic1f76ac12011-11-30 23:56:52 +000053
Stefano Babicf39fd592012-08-29 01:21:59 +000054#define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW 0x07
Stefano Babic1f76ac12011-11-30 23:56:52 +000055
56/*
57 * Board NAND Info.
58 */
59#define CONFIG_SYS_NAND_BASE NAND_BASE /* physical address */
60 /* to access */
61 /* nand at CS0 */
62
63#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of */
64 /* NAND devices */
Stefano Babic1f76ac12011-11-30 23:56:52 +000065
Stefano Babic1f76ac12011-11-30 23:56:52 +000066/*
67 * Miscellaneous configurable options
68 */
Stefano Babic1f76ac12011-11-30 23:56:52 +000069#define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */
70
Stefano Babic1f76ac12011-11-30 23:56:52 +000071#define CONFIG_SYS_MAXARGS 32 /* max number of command */
72 /* args */
Stefano Babic1f76ac12011-11-30 23:56:52 +000073
74/*
75 * AM3517 has 12 GP timers, they can be driven by the system clock
76 * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK).
77 * This rate is divided by a local divisor.
78 */
79#define CONFIG_SYS_TIMERBASE OMAP34XX_GPT2
80#define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */
Stefano Babic1f76ac12011-11-30 23:56:52 +000081
82/*
Stefano Babic1f76ac12011-11-30 23:56:52 +000083 * Physical Memory Map
84 */
Stefano Babic1f76ac12011-11-30 23:56:52 +000085#define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0
Stefano Babic1f76ac12011-11-30 23:56:52 +000086#define PHYS_SDRAM_2 OMAP34XX_SDRC_CS1
87
88/*
89 * FLASH and environment organization
90 */
91
92/* **** PISMO SUPPORT *** */
Stefano Babic1f76ac12011-11-30 23:56:52 +000093
94/* Redundant Environment */
95#define CONFIG_SYS_ENV_SECT_SIZE (128 << 10) /* 128 KiB */
Stefano Babic1f76ac12011-11-30 23:56:52 +000096
97#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
98#define CONFIG_SYS_INIT_RAM_ADDR 0x4020f800
99#define CONFIG_SYS_INIT_RAM_SIZE 0x800
100#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \
101 CONFIG_SYS_INIT_RAM_SIZE - \
102 GENERATED_GBL_DATA_SIZE)
103
104/*
105 * ethernet support, EMAC
106 *
107 */
Stefano Babic1f76ac12011-11-30 23:56:52 +0000108#define CONFIG_NET_RETRY_COUNT 10
Stefano Babic1f76ac12011-11-30 23:56:52 +0000109
110/* Defines for SPL */
Stefano Babic1f76ac12011-11-30 23:56:52 +0000111#define CONFIG_SPL_CONSOLE
Jeroen Hofstee64407af2013-12-21 18:03:09 +0100112#define CONFIG_SPL_NAND_SOFTECC
Stefano Babic1f76ac12011-11-30 23:56:52 +0000113#define CONFIG_SPL_NAND_WORKSPACE 0x8f07f000 /* below BSS */
114
Tom Rinicfff4aa2016-08-26 13:30:43 -0400115#define CONFIG_SPL_MAX_SIZE (SRAM_SCRATCH_SPACE_ADDR - \
116 CONFIG_SPL_TEXT_BASE)
Stefano Babice0faf3c2016-06-14 09:13:37 +0200117#define CONFIG_SPL_STACK LOW_LEVEL_SRAM_STACK
Stefano Babic1f76ac12011-11-30 23:56:52 +0000118
119#define CONFIG_SYS_SPL_MALLOC_START 0x8f000000
120#define CONFIG_SYS_SPL_MALLOC_SIZE 0x80000
121#define CONFIG_SPL_BSS_START_ADDR 0x8f080000 /* end of RAM */
122#define CONFIG_SPL_BSS_MAX_SIZE 0x80000
123
Stefano Babice0faf3c2016-06-14 09:13:37 +0200124#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img"
125
126/* FAT */
127#define CONFIG_SPL_FS_LOAD_KERNEL_NAME "uImage"
128#define CONFIG_SPL_FS_LOAD_ARGS_NAME "args"
129
130/* RAW SD card / eMMC */
131#define CONFIG_SYS_MMCSD_RAW_MODE_KERNEL_SECTOR 0x900 /* address 0x120000 */
132#define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTOR 0x80 /* address 0x10000 */
133#define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTORS 0x80 /* 64KiB */
134
Stefano Babic1f76ac12011-11-30 23:56:52 +0000135/* NAND boot config */
136#define CONFIG_SYS_NAND_PAGE_COUNT 64
137#define CONFIG_SYS_NAND_PAGE_SIZE 2048
138#define CONFIG_SYS_NAND_OOBSIZE 64
139#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
140#define CONFIG_SYS_NAND_5_ADDR_CYCLE
141#define CONFIG_SYS_NAND_BAD_BLOCK_POS 0
142#define CONFIG_SYS_NAND_ECCPOS {40, 41, 42, 43, 44, 45, 46, 47,\
143 48, 49, 50, 51, 52, 53, 54, 55,\
144 56, 57, 58, 59, 60, 61, 62, 63}
145#define CONFIG_SYS_NAND_ECCSIZE 256
146#define CONFIG_SYS_NAND_ECCBYTES 3
pekon gupta3ef49732013-11-18 19:03:01 +0530147#define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_HAM1_CODE_SW
Stefano Babic1f76ac12011-11-30 23:56:52 +0000148
Stefano Babic1f76ac12011-11-30 23:56:52 +0000149#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE
150
151#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x80000
152#define CONFIG_SYS_NAND_U_BOOT_SIZE 0x80000
153
Stefano Babic1f76ac12011-11-30 23:56:52 +0000154/* Setup MTD for NAND on the SOM */
Stefano Babic1f76ac12011-11-30 23:56:52 +0000155
Stefano Babic1f76ac12011-11-30 23:56:52 +0000156#define CONFIG_TAM3517_SETTINGS \
157 "netdev=eth0\0" \
158 "nandargs=setenv bootargs root=${nandroot} " \
159 "rootfstype=${nandrootfstype}\0" \
160 "nfsargs=setenv bootargs root=/dev/nfs rw " \
161 "nfsroot=${serverip}:${rootpath}\0" \
162 "ramargs=setenv bootargs root=/dev/ram rw\0" \
163 "addip_sta=setenv bootargs ${bootargs} " \
164 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
165 ":${hostname}:${netdev}:off panic=1\0" \
166 "addip_dyn=setenv bootargs ${bootargs} ip=dhcp\0" \
167 "addip=if test -n ${ipdyn};then run addip_dyn;" \
168 "else run addip_sta;fi\0" \
169 "addmtd=setenv bootargs ${bootargs} ${mtdparts}\0" \
170 "addtty=setenv bootargs ${bootargs}" \
171 " console=ttyO0,${baudrate}\0" \
172 "addmisc=setenv bootargs ${bootargs} ${misc}\0" \
173 "loadaddr=82000000\0" \
174 "kernel_addr_r=82000000\0" \
Mario Six790d8442018-03-28 14:38:20 +0200175 "hostname=" CONFIG_HOSTNAME "\0" \
176 "bootfile=" CONFIG_HOSTNAME "/uImage\0" \
Stefano Babic1f76ac12011-11-30 23:56:52 +0000177 "flash_self=run ramargs addip addtty addmtd addmisc;" \
178 "bootm ${kernel_addr} ${ramdisk_addr}\0" \
179 "flash_nfs=run nfsargs addip addtty addmtd addmisc;" \
180 "bootm ${kernel_addr}\0" \
181 "nandboot=run nandargs addip addtty addmtd addmisc;" \
182 "nand read ${kernel_addr_r} kernel\0" \
183 "bootm ${kernel_addr_r}\0" \
184 "net_nfs=tftp ${kernel_addr_r} ${bootfile}; " \
185 "run nfsargs addip addtty addmtd addmisc;" \
186 "bootm ${kernel_addr_r}\0" \
187 "net_self=if run net_self_load;then " \
188 "run ramargs addip addtty addmtd addmisc;" \
189 "bootm ${kernel_addr_r} ${ramdisk_addr_r};" \
190 "else echo Images not loades;fi\0" \
Mario Six790d8442018-03-28 14:38:20 +0200191 "u-boot=" CONFIG_HOSTNAME "/u-boot.img\0" \
Stefano Babic1f76ac12011-11-30 23:56:52 +0000192 "load=tftp ${loadaddr} ${u-boot}\0" \
193 "loadmlo=tftp ${loadaddr} ${mlo}\0" \
Mario Six790d8442018-03-28 14:38:20 +0200194 "mlo=" CONFIG_HOSTNAME "/MLO\0" \
Stefano Babic1f76ac12011-11-30 23:56:52 +0000195 "uboot_addr=0x80000\0" \
196 "update=nandecc sw;nand erase ${uboot_addr} 100000;" \
197 "nand write ${loadaddr} ${uboot_addr} 80000\0" \
198 "updatemlo=nandecc hw;nand erase 0 20000;" \
199 "nand write ${loadaddr} 0 20000\0" \
200 "upd=if run load;then echo Updating u-boot;if run update;" \
201 "then echo U-Boot updated;" \
202 "else echo Error updating u-boot !;" \
203 "echo Board without bootloader !!;" \
204 "fi;" \
205 "else echo U-Boot not downloaded..exiting;fi\0" \
206
Stefano Babicf39fd592012-08-29 01:21:59 +0000207/*
208 * this is common code for all TAM3517 boards.
209 * MAC address is stored from manufacturer in
210 * I2C EEPROM
211 */
212#if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__))
Stefano Babicf39fd592012-08-29 01:21:59 +0000213/*
214 * The I2C EEPROM on the TAM3517 contains
215 * mac address and production data
216 */
217struct tam3517_module_info {
218 char customer[48];
219 char product[48];
220
221 /*
222 * bit 0~47 : sequence number
223 * bit 48~55 : week of year, from 0.
224 * bit 56~63 : year
225 */
226 unsigned long long sequence_number;
227
228 /*
229 * bit 0~7 : revision fixed
230 * bit 8~15 : revision major
231 * bit 16~31 : TNxxx
232 */
233 unsigned int revision;
234 unsigned char eth_addr[4][8];
235 unsigned char _rev[100];
236};
237
Stefano Babic0a152e62012-11-23 05:19:25 +0000238#define TAM3517_READ_EEPROM(info, ret) \
239do { \
Tom Rinia7a9bc02021-08-18 23:12:29 -0400240 i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE); \
Stefano Babicf39fd592012-08-29 01:21:59 +0000241 if (eeprom_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0, \
Stefano Babic0a152e62012-11-23 05:19:25 +0000242 (void *)info, sizeof(*info))) \
243 ret = 1; \
244 else \
245 ret = 0; \
246} while (0)
247
248#define TAM3517_READ_MAC_FROM_EEPROM(info) \
249do { \
250 char buf[80], ethname[20]; \
251 int i; \
Stefano Babicf39fd592012-08-29 01:21:59 +0000252 memset(buf, 0, sizeof(buf)); \
Stefano Babic0a152e62012-11-23 05:19:25 +0000253 for (i = 0 ; i < ARRAY_SIZE((info)->eth_addr); i++) { \
Stefano Babicf39fd592012-08-29 01:21:59 +0000254 sprintf(buf, "%02X:%02X:%02X:%02X:%02X:%02X", \
Stefano Babic0a152e62012-11-23 05:19:25 +0000255 (info)->eth_addr[i][5], \
256 (info)->eth_addr[i][4], \
257 (info)->eth_addr[i][3], \
258 (info)->eth_addr[i][2], \
259 (info)->eth_addr[i][1], \
260 (info)->eth_addr[i][0]); \
Stefano Babicf39fd592012-08-29 01:21:59 +0000261 \
262 if (i) \
263 sprintf(ethname, "eth%daddr", i); \
264 else \
Ben Whitten34fd6c92015-12-30 13:05:58 +0000265 strcpy(ethname, "ethaddr"); \
Stefano Babicf39fd592012-08-29 01:21:59 +0000266 printf("Setting %s from EEPROM with %s\n", ethname, buf);\
Simon Glass6a38e412017-08-03 12:22:09 -0600267 env_set(ethname, buf); \
Stefano Babicf39fd592012-08-29 01:21:59 +0000268 } \
269} while (0)
Stefano Babic0a152e62012-11-23 05:19:25 +0000270
271/* The following macros are taken from Technexion's documentation */
272#define TAM3517_sequence_number(info) \
273 ((info)->sequence_number % 0x1000000000000LL)
274#define TAM3517_week_of_year(info) (((info)->sequence_number >> 48) % 0x100)
275#define TAM3517_year(info) ((info)->sequence_number >> 56)
276#define TAM3517_revision_fixed(info) ((info)->revision % 0x100)
277#define TAM3517_revision_major(info) (((info)->revision >> 8) % 0x100)
278#define TAM3517_revision_tn(info) ((info)->revision >> 16)
279
280#define TAM3517_PRINT_SOM_INFO(info) \
281do { \
282 printf("Vendor:%s\n", (info)->customer); \
283 printf("SOM: %s\n", (info)->product); \
284 printf("SeqNr: %02llu%02llu%012llu\n", \
285 TAM3517_year(info), \
286 TAM3517_week_of_year(info), \
287 TAM3517_sequence_number(info)); \
288 printf("Rev: TN%u %u.%u\n", \
289 TAM3517_revision_tn(info), \
290 TAM3517_revision_major(info), \
291 TAM3517_revision_fixed(info)); \
292} while (0)
293
Stefano Babicf39fd592012-08-29 01:21:59 +0000294#endif
295
Stefano Babic1f76ac12011-11-30 23:56:52 +0000296#endif /* __TAM3517_H */