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Tom Rini10e47792018-05-06 17:58:06 -04001/* SPDX-License-Identifier: GPL-2.0+ */
Tom Warren22425c92015-02-12 15:01:49 -07002/*
3 * (C) Copyright 2013-2015
4 * NVIDIA Corporation <www.nvidia.com>
Tom Warren22425c92015-02-12 15:01:49 -07005 */
6
7#ifndef _TEGRA210_COMMON_H_
8#define _TEGRA210_COMMON_H_
9
10#include "tegra-common.h"
11
Tom Warren22425c92015-02-12 15:01:49 -070012/*
13 * NS16550 Configuration
14 */
15#define V_NS16550_CLK 408000000 /* 408MHz (pllp_out0) */
16
Tom Warren22425c92015-02-12 15:01:49 -070017/*
18 * Memory layout for where various images get loaded by boot scripts:
19 *
20 * scriptaddr can be pretty much anywhere that doesn't conflict with something
21 * else. Put it above BOOTMAPSZ to eliminate conflicts.
22 *
23 * pxefile_addr_r can be pretty much anywhere that doesn't conflict with
24 * something else. Put it above BOOTMAPSZ to eliminate conflicts.
25 *
26 * kernel_addr_r must be within the first 128M of RAM in order for the
27 * kernel's CONFIG_AUTO_ZRELADDR option to work. Since the kernel will
28 * decompress itself to 0x8000 after the start of RAM, kernel_addr_r
29 * should not overlap that area, or the kernel will have to copy itself
30 * somewhere else before decompression. Similarly, the address of any other
31 * data passed to the kernel shouldn't overlap the start of RAM. Pushing
32 * this up to 16M allows for a sizable kernel to be decompressed below the
33 * compressed load address.
34 *
35 * fdt_addr_r simply shouldn't overlap anything else. Choosing 32M allows for
36 * the compressed kernel to be up to 16M too.
37 *
38 * ramdisk_addr_r simply shouldn't overlap anything else. Choosing 33M allows
39 * for the FDT/DTB to be up to 1M, which is hopefully plenty.
40 */
Stephen Warren5eed1a52015-08-07 16:12:43 -060041#define CONFIG_LOADADDR 0x80080000
Tom Warren22425c92015-02-12 15:01:49 -070042#define MEM_LAYOUT_ENV_SETTINGS \
43 "scriptaddr=0x90000000\0" \
44 "pxefile_addr_r=0x90100000\0" \
45 "kernel_addr_r=" __stringify(CONFIG_LOADADDR) "\0" \
Peter Robinson637ac012020-04-02 00:28:54 +010046 "fdtfile=" FDTFILE "\0" \
Tom Warrenfbb47712020-03-16 17:01:43 -070047 "fdt_addr_r=0x83000000\0" \
48 "ramdisk_addr_r=0x83200000\0"
Tom Warren22425c92015-02-12 15:01:49 -070049
Tom Warren22425c92015-02-12 15:01:49 -070050/* For USB EHCI controller */
51#define CONFIG_EHCI_IS_TDI
52#define CONFIG_USB_EHCI_TXFIFO_THRESH 0x10
Tom Warren22425c92015-02-12 15:01:49 -070053
Alexandre Courbot7f936d42015-07-09 16:33:00 +090054/* GPU needs setup */
55#define CONFIG_TEGRA_GPU
56
Tom Warren22425c92015-02-12 15:01:49 -070057#endif /* _TEGRA210_COMMON_H_ */