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Tom Rini10e47792018-05-06 17:58:06 -04001/* SPDX-License-Identifier: GPL-2.0+ */
Phil Edworthy04a62752012-05-15 22:15:51 +00002/*
3 * Configuation settings for the Renesas RSK2+SH7269 board
4 *
5 * Copyright (C) 2012 Renesas Electronics Europe Ltd.
6 * Copyright (C) 2012 Phil Edworthy
Phil Edworthy04a62752012-05-15 22:15:51 +00007 */
8
9#ifndef __RSK7269_H
10#define __RSK7269_H
11
Phil Edworthy04a62752012-05-15 22:15:51 +000012#define CONFIG_CPU_SH7269 1
Phil Edworthy04a62752012-05-15 22:15:51 +000013
Vladimir Zapolskiy5e72b842016-11-28 00:15:30 +020014#define CONFIG_DISPLAY_BOARDINFO
15
Phil Edworthy04a62752012-05-15 22:15:51 +000016#define CONFIG_SYS_BAUDRATE_TABLE { CONFIG_BAUDRATE }
17
Phil Edworthy04a62752012-05-15 22:15:51 +000018#define CONFIG_SYS_PBSIZE 256 /* Print Buffer Size */
Phil Edworthy04a62752012-05-15 22:15:51 +000019
20/* Serial */
Phil Edworthy04a62752012-05-15 22:15:51 +000021#define CONFIG_CONS_SCIF7
22
23/* Memory */
24/* u-boot relocated to top 256KB of ram */
Phil Edworthy04a62752012-05-15 22:15:51 +000025#define CONFIG_SYS_SDRAM_BASE 0x0C000000
26#define CONFIG_SYS_SDRAM_SIZE (32 * 1024 * 1024)
27
28#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE
29#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_TEXT_BASE - 0x100000)
30#define CONFIG_SYS_MALLOC_LEN (256 * 1024)
31#define CONFIG_SYS_MONITOR_LEN (128 * 1024)
32#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 4*1024*1024)
33
34/* NOR Flash */
Phil Edworthy04a62752012-05-15 22:15:51 +000035#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
36#define CONFIG_SYS_FLASH_BASE 0x20000000 /* Non-cached */
37#define CONFIG_SYS_MAX_FLASH_BANKS 1
38#define CONFIG_SYS_MAX_FLASH_SECT 512
39
Phil Edworthy04a62752012-05-15 22:15:51 +000040#define CONFIG_ENV_OFFSET (128 * 1024)
41#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_ENV_OFFSET)
42#define CONFIG_ENV_SECT_SIZE (64 * 1024)
43#define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE
44
45/* Board Clock */
46#define CONFIG_SYS_CLK_FREQ 66125000
Nobuhiro Iwamatsue6984492013-08-21 16:11:21 +090047#define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ
Phil Edworthy04a62752012-05-15 22:15:51 +000048#define CMT_CLK_DIVIDER 32 /* 8 (default), 32, 128 or 512 */
Nobuhiro Iwamatsubefb5cc2014-01-08 14:57:30 +090049#define CONFIG_SH_CMT_CLK_FREQ (CONFIG_SYS_CLK_FREQ / CMT_CLK_DIVIDER)
Phil Edworthy04a62752012-05-15 22:15:51 +000050
Phil Edworthy04a62752012-05-15 22:15:51 +000051#endif /* __RSK7269_H */