Tom Rini | 10e4779 | 2018-05-06 17:58:06 -0400 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0+ */ |
Holger Brunck | 3bf8b98 | 2012-03-21 13:42:46 +0100 | [diff] [blame] | 2 | /* |
| 3 | * (C) Copyright 2012 |
| 4 | * Holger Brunck, Keymile GmbH Hannover, <holger.brunck@keymile.com> |
| 5 | * Christian Herzig, Keymile AG Switzerland, <christian.herzig@keymile.com> |
Holger Brunck | 3bf8b98 | 2012-03-21 13:42:46 +0100 | [diff] [blame] | 6 | */ |
| 7 | |
| 8 | #ifndef __CONFIG_H |
| 9 | #define __CONFIG_H |
| 10 | |
| 11 | /* KMBEC FPGA (PRIO) */ |
| 12 | #define CONFIG_SYS_KMBEC_FPGA_BASE 0xE8000000 |
| 13 | #define CONFIG_SYS_KMBEC_FPGA_SIZE 64 |
| 14 | |
| 15 | #if defined CONFIG_KMETER1 |
Mario Six | 790d844 | 2018-03-28 14:38:20 +0200 | [diff] [blame] | 16 | #define CONFIG_HOSTNAME "kmeter1" |
Holger Brunck | 3bf8b98 | 2012-03-21 13:42:46 +0100 | [diff] [blame] | 17 | #define CONFIG_KM_BOARD_NAME "kmeter1" |
| 18 | #define CONFIG_KM_DEF_NETDEV "netdev=eth2\0" |
| 19 | #elif defined CONFIG_KMCOGE5NE |
Mario Six | 790d844 | 2018-03-28 14:38:20 +0200 | [diff] [blame] | 20 | #define CONFIG_HOSTNAME "kmcoge5ne" |
Holger Brunck | 3bf8b98 | 2012-03-21 13:42:46 +0100 | [diff] [blame] | 21 | #define CONFIG_KM_BOARD_NAME "kmcoge5ne" |
| 22 | #define CONFIG_KM_DEF_NETDEV "netdev=eth1\0" |
Holger Brunck | 154772c | 2013-01-21 03:55:23 +0000 | [diff] [blame] | 23 | #define CONFIG_NAND_ECC_BCH |
Holger Brunck | 3bf8b98 | 2012-03-21 13:42:46 +0100 | [diff] [blame] | 24 | #define CONFIG_NAND_KMETER1 |
| 25 | #define CONFIG_SYS_MAX_NAND_DEVICE 1 |
| 26 | #define NAND_MAX_CHIPS 1 |
| 27 | #define CONFIG_SYS_NAND_BASE CONFIG_SYS_KMBEC_FPGA_BASE /* PRIO_BASE_ADDRESS */ |
| 28 | |
| 29 | #define CONFIG_KM_UBI_PARTITION_NAME_BOOT "ubi0" |
| 30 | #define CONFIG_KM_UBI_PARTITION_NAME_APP "ubi1" |
Holger Brunck | 3bf8b98 | 2012-03-21 13:42:46 +0100 | [diff] [blame] | 31 | #else |
| 32 | #error ("Board not supported") |
| 33 | #endif |
| 34 | |
| 35 | /* |
| 36 | * High Level Configuration Options |
| 37 | */ |
| 38 | #define CONFIG_QE /* Has QE */ |
| 39 | #define CONFIG_MPC8360 /* MPC8360 CPU specific */ |
| 40 | |
Holger Brunck | 3bf8b98 | 2012-03-21 13:42:46 +0100 | [diff] [blame] | 41 | /* include common defines/options for all 83xx Keymile boards */ |
| 42 | #include "km/km83xx-common.h" |
| 43 | |
| 44 | /* |
| 45 | * System IO Setup |
| 46 | */ |
| 47 | #define CONFIG_SYS_SICRH (SICRH_UC1EOBI | SICRH_UC2E1OBI) |
| 48 | |
| 49 | /* |
| 50 | * Hardware Reset Configuration Word |
| 51 | */ |
| 52 | #define CONFIG_SYS_HRCW_LOW (\ |
| 53 | HRCWL_CSB_TO_CLKIN_4X1 | \ |
| 54 | HRCWL_CORE_TO_CSB_2X1 | \ |
| 55 | HRCWL_CE_PLL_VCO_DIV_2 | \ |
| 56 | HRCWL_CE_TO_PLL_1X6) |
| 57 | |
| 58 | #define CONFIG_SYS_HRCW_HIGH (\ |
| 59 | HRCWH_CORE_ENABLE | \ |
| 60 | HRCWH_FROM_0X00000100 | \ |
| 61 | HRCWH_BOOTSEQ_DISABLE | \ |
| 62 | HRCWH_SW_WATCHDOG_DISABLE | \ |
| 63 | HRCWH_ROM_LOC_LOCAL_16BIT | \ |
| 64 | HRCWH_BIG_ENDIAN | \ |
| 65 | HRCWH_LALE_EARLY | \ |
| 66 | HRCWH_LDP_CLEAR) |
| 67 | |
| 68 | /** |
| 69 | * DDR RAM settings |
| 70 | */ |
| 71 | #define CONFIG_SYS_DDR_SDRAM_CFG (\ |
| 72 | SDRAM_CFG_SDRAM_TYPE_DDR2 | \ |
| 73 | SDRAM_CFG_SREN | \ |
| 74 | SDRAM_CFG_HSE) |
| 75 | |
| 76 | #define CONFIG_SYS_DDR_SDRAM_CFG2 0x00401000 |
| 77 | |
| 78 | #ifdef CONFIG_KMCOGE5NE |
| 79 | /** |
| 80 | * KMCOGE5NE has 512 MB RAM |
| 81 | */ |
| 82 | #define CONFIG_SYS_DDR_CS0_CONFIG (\ |
| 83 | CSCONFIG_EN | \ |
| 84 | CSCONFIG_AP | \ |
Valentin Longchamp | 9c36b47 | 2015-11-17 10:53:33 +0100 | [diff] [blame] | 85 | CSCONFIG_ODT_WR_ONLY_CURRENT | \ |
Holger Brunck | 3bf8b98 | 2012-03-21 13:42:46 +0100 | [diff] [blame] | 86 | CSCONFIG_BANK_BIT_3 | \ |
| 87 | CSCONFIG_ROW_BIT_13 | \ |
| 88 | CSCONFIG_COL_BIT_10) |
| 89 | #else |
| 90 | #define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN | CSCONFIG_AP | \ |
| 91 | CSCONFIG_ROW_BIT_13 | \ |
| 92 | CSCONFIG_COL_BIT_10 | \ |
Valentin Longchamp | 9c36b47 | 2015-11-17 10:53:33 +0100 | [diff] [blame] | 93 | CSCONFIG_ODT_WR_ONLY_CURRENT) |
Holger Brunck | 3bf8b98 | 2012-03-21 13:42:46 +0100 | [diff] [blame] | 94 | #endif |
| 95 | |
| 96 | #define CONFIG_SYS_DDR_CLK_CNTL (\ |
| 97 | DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05) |
| 98 | |
| 99 | #define CONFIG_SYS_DDR_INTERVAL (\ |
| 100 | (0x080 << SDRAM_INTERVAL_BSTOPRE_SHIFT) | \ |
| 101 | (0x203 << SDRAM_INTERVAL_REFINT_SHIFT)) |
| 102 | |
| 103 | #define CONFIG_SYS_DDR_CS0_BNDS 0x0000007f |
| 104 | |
| 105 | #define CONFIG_SYS_DDRCDR (\ |
| 106 | DDRCDR_EN | \ |
| 107 | DDRCDR_Q_DRN) |
| 108 | #define CONFIG_SYS_DDR_MODE 0x47860452 |
| 109 | #define CONFIG_SYS_DDR_MODE2 0x8080c000 |
| 110 | |
| 111 | #define CONFIG_SYS_DDR_TIMING_0 (\ |
| 112 | (2 << TIMING_CFG0_MRS_CYC_SHIFT) | \ |
| 113 | (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) | \ |
| 114 | (6 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) | \ |
| 115 | (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) | \ |
| 116 | (0 << TIMING_CFG0_WWT_SHIFT) | \ |
| 117 | (0 << TIMING_CFG0_RRT_SHIFT) | \ |
| 118 | (0 << TIMING_CFG0_WRT_SHIFT) | \ |
| 119 | (0 << TIMING_CFG0_RWT_SHIFT)) |
| 120 | |
| 121 | #define CONFIG_SYS_DDR_TIMING_1 ((TIMING_CFG1_CASLAT_50) | \ |
| 122 | (2 << TIMING_CFG1_WRTORD_SHIFT) | \ |
| 123 | (2 << TIMING_CFG1_ACTTOACT_SHIFT) | \ |
| 124 | (3 << TIMING_CFG1_WRREC_SHIFT) | \ |
| 125 | (7 << TIMING_CFG1_REFREC_SHIFT) | \ |
| 126 | (3 << TIMING_CFG1_ACTTORW_SHIFT) | \ |
| 127 | (8 << TIMING_CFG1_ACTTOPRE_SHIFT) | \ |
| 128 | (3 << TIMING_CFG1_PRETOACT_SHIFT)) |
| 129 | |
| 130 | #define CONFIG_SYS_DDR_TIMING_2 (\ |
| 131 | (0xa << TIMING_CFG2_FOUR_ACT_SHIFT) | \ |
| 132 | (3 << TIMING_CFG2_CKE_PLS_SHIFT) | \ |
| 133 | (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) | \ |
| 134 | (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) | \ |
| 135 | (4 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) | \ |
| 136 | (5 << TIMING_CFG2_CPO_SHIFT) | \ |
| 137 | (0 << TIMING_CFG2_ADD_LAT_SHIFT)) |
| 138 | |
| 139 | #define CONFIG_SYS_DDR_TIMING_3 0x00000000 |
| 140 | |
| 141 | /* EEprom support */ |
| 142 | #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 |
| 143 | |
| 144 | /* |
| 145 | * Local Bus Configuration & Clock Setup |
| 146 | */ |
| 147 | #define CONFIG_SYS_LCRR_DBYP LCRR_DBYP |
| 148 | #define CONFIG_SYS_LCRR_EADC LCRR_EADC_2 |
| 149 | #define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_4 |
| 150 | |
| 151 | /* |
| 152 | * PAXE on the local bus CS3 |
| 153 | */ |
| 154 | #define CONFIG_SYS_PAXE_BASE 0xA0000000 |
| 155 | #define CONFIG_SYS_PAXE_SIZE 256 |
| 156 | |
| 157 | #define CONFIG_SYS_LBLAWBAR3_PRELIM CONFIG_SYS_PAXE_BASE |
| 158 | |
| 159 | #define CONFIG_SYS_LBLAWAR3_PRELIM 0x8000001C /* 512MB window size */ |
| 160 | |
| 161 | #define CONFIG_SYS_BR3_PRELIM (\ |
| 162 | CONFIG_SYS_PAXE_BASE | \ |
| 163 | (1 << BR_PS_SHIFT) | \ |
| 164 | BR_V) |
| 165 | |
| 166 | #define CONFIG_SYS_OR3_PRELIM (\ |
| 167 | MEG_TO_AM(CONFIG_SYS_PAXE_SIZE) | \ |
| 168 | OR_GPCM_CSNT | \ |
| 169 | OR_GPCM_ACS_DIV2 | \ |
| 170 | OR_GPCM_SCY_2 | \ |
| 171 | OR_GPCM_TRLX | \ |
| 172 | OR_GPCM_EAD) |
| 173 | |
| 174 | #ifdef CONFIG_KMCOGE5NE |
| 175 | /* |
| 176 | * BFTIC3 on the local bus CS4 |
| 177 | */ |
| 178 | #define CONFIG_SYS_BFTIC3_BASE 0xB0000000 |
| 179 | #define CONFIG_SYS_BFTIC3_SIZE 256 |
| 180 | |
| 181 | #define CONFIG_SYS_BR4_PRELIM (\ |
| 182 | CONFIG_SYS_BFTIC3_BASE |\ |
| 183 | (1 << BR_PS_SHIFT) | \ |
| 184 | BR_V) |
| 185 | |
| 186 | #define CONFIG_SYS_OR4_PRELIM (\ |
| 187 | MEG_TO_AM(CONFIG_SYS_BFTIC3_SIZE) |\ |
| 188 | OR_GPCM_CSNT | \ |
| 189 | OR_GPCM_ACS_DIV2 |\ |
| 190 | OR_GPCM_SCY_2 |\ |
| 191 | OR_GPCM_TRLX |\ |
| 192 | OR_GPCM_EAD) |
| 193 | #endif |
| 194 | |
| 195 | /* |
| 196 | * MMU Setup |
| 197 | */ |
| 198 | |
| 199 | /* PAXE: icache cacheable, but dcache-inhibit and guarded */ |
| 200 | #define CONFIG_SYS_IBAT5L (\ |
| 201 | CONFIG_SYS_PAXE_BASE | \ |
| 202 | BATL_PP_10 | \ |
| 203 | BATL_MEMCOHERENCE) |
| 204 | |
| 205 | #define CONFIG_SYS_IBAT5U (\ |
| 206 | CONFIG_SYS_PAXE_BASE | \ |
| 207 | BATU_BL_256M | \ |
| 208 | BATU_VS | \ |
| 209 | BATU_VP) |
| 210 | |
| 211 | #define CONFIG_SYS_DBAT5L (\ |
| 212 | CONFIG_SYS_PAXE_BASE | \ |
| 213 | BATL_PP_10 | \ |
| 214 | BATL_CACHEINHIBIT | \ |
| 215 | BATL_GUARDEDSTORAGE) |
| 216 | |
| 217 | #define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U |
| 218 | |
Holger Brunck | 3bf8b98 | 2012-03-21 13:42:46 +0100 | [diff] [blame] | 219 | #ifdef CONFIG_KMCOGE5NE |
| 220 | /* BFTIC3: icache cacheable, but dcache-inhibit and guarded */ |
| 221 | #define CONFIG_SYS_IBAT6L (\ |
| 222 | CONFIG_SYS_BFTIC3_BASE | \ |
| 223 | BATL_PP_10 | \ |
| 224 | BATL_MEMCOHERENCE) |
| 225 | |
| 226 | #define CONFIG_SYS_IBAT6U (\ |
| 227 | CONFIG_SYS_BFTIC3_BASE | \ |
| 228 | BATU_BL_256M | \ |
| 229 | BATU_VS | \ |
| 230 | BATU_VP) |
| 231 | |
| 232 | #define CONFIG_SYS_DBAT6L (\ |
| 233 | CONFIG_SYS_BFTIC3_BASE | \ |
| 234 | BATL_PP_10 | \ |
| 235 | BATL_CACHEINHIBIT | \ |
| 236 | BATL_GUARDEDSTORAGE) |
| 237 | |
| 238 | #define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U |
| 239 | |
| 240 | /* DDR/LBC SDRAM next 256M: cacheable */ |
| 241 | #define CONFIG_SYS_IBAT7L (\ |
| 242 | CONFIG_SYS_SDRAM_BASE2 |\ |
| 243 | BATL_PP_10 |\ |
| 244 | BATL_CACHEINHIBIT |\ |
| 245 | BATL_GUARDEDSTORAGE) |
| 246 | |
| 247 | #define CONFIG_SYS_IBAT7U (\ |
| 248 | CONFIG_SYS_SDRAM_BASE2 |\ |
| 249 | BATU_BL_256M |\ |
| 250 | BATU_VS |\ |
| 251 | BATU_VP) |
Thomas Herzmann | 94fbf52 | 2012-05-04 10:55:56 +0200 | [diff] [blame] | 252 | /* enable POST tests */ |
| 253 | #define CONFIG_POST (CONFIG_SYS_POST_MEMORY|CONFIG_SYS_POST_MEM_REGIONS) |
| 254 | #define CONFIG_POST_EXTERNAL_WORD_FUNCS /* use own functions, not generic */ |
| 255 | #define CPM_POST_WORD_ADDR CONFIG_SYS_MEMTEST_END |
| 256 | #define CONFIG_TESTPIN_REG gprt3 /* for kmcoge5ne */ |
| 257 | #define CONFIG_TESTPIN_MASK 0x20 /* for kmcoge5ne */ |
Thomas Herzmann | 94fbf52 | 2012-05-04 10:55:56 +0200 | [diff] [blame] | 258 | |
Holger Brunck | 3bf8b98 | 2012-03-21 13:42:46 +0100 | [diff] [blame] | 259 | #else |
| 260 | #define CONFIG_SYS_IBAT6L (0) |
| 261 | #define CONFIG_SYS_IBAT6U (0) |
| 262 | #define CONFIG_SYS_IBAT7L (0) |
| 263 | #define CONFIG_SYS_IBAT7U (0) |
| 264 | #define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L |
| 265 | #define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U |
| 266 | #endif |
| 267 | |
| 268 | #define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L |
| 269 | #define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U |
| 270 | |
| 271 | #endif /* CONFIG */ |