blob: b6c5cad4338463c8c56af87b0423f8faa1a5e0d6 [file] [log] [blame]
Tom Rini10e47792018-05-06 17:58:06 -04001/* SPDX-License-Identifier: GPL-2.0 */
Nobuhiro Iwamatsuae870122014-11-06 16:30:56 +09002/*
3 * include/configs/rcar-gen2-common.h
4 *
5 * Copyright (C) 2013,2014 Renesas Electronics Corporation
Nobuhiro Iwamatsuae870122014-11-06 16:30:56 +09006 */
7
8#ifndef __RCAR_GEN2_COMMON_H
9#define __RCAR_GEN2_COMMON_H
10
11#include <asm/arch/rmobile.h>
12
Nobuhiro Iwamatsuae870122014-11-06 16:30:56 +090013#define CONFIG_CMDLINE_TAG
14#define CONFIG_SETUP_MEMORY_TAGS
15#define CONFIG_INITRD_TAG
Nobuhiro Iwamatsuae870122014-11-06 16:30:56 +090016
Marek Vasutcf0f72c2018-02-26 20:19:08 +010017#ifdef CONFIG_SPL
18#define CONFIG_SPL_TARGET "spl/u-boot-spl.srec"
19#endif
20
Marek Vasuta5bbe262018-01-07 19:32:56 +010021#ifndef CONFIG_PINCTRL_PFC
Nobuhiro Iwamatsuae870122014-11-06 16:30:56 +090022#define CONFIG_SH_GPIO_PFC
Marek Vasuta5bbe262018-01-07 19:32:56 +010023#endif
Nobuhiro Iwamatsuae870122014-11-06 16:30:56 +090024
25/* console */
Nobuhiro Iwamatsuae870122014-11-06 16:30:56 +090026#define CONFIG_SYS_PBSIZE 256
Nobuhiro Iwamatsuae870122014-11-06 16:30:56 +090027#define CONFIG_SYS_BAUDRATE_TABLE { 38400, 115200 }
28
29#define CONFIG_SYS_SDRAM_BASE (RCAR_GEN2_SDRAM_BASE)
30#define CONFIG_SYS_SDRAM_SIZE (RCAR_GEN2_UBOOT_SDRAM_SIZE)
Marek Vasut0e60f742018-05-31 15:12:53 +020031#define CONFIG_SYS_LOAD_ADDR 0x50000000
32#define CONFIG_LOADADDR CONFIG_SYS_LOAD_ADDR
Nobuhiro Iwamatsuae870122014-11-06 16:30:56 +090033
34#define CONFIG_SYS_MONITOR_BASE 0x00000000
35#define CONFIG_SYS_MONITOR_LEN (256 * 1024)
36#define CONFIG_SYS_MALLOC_LEN (1 * 1024 * 1024)
Nobuhiro Iwamatsuae870122014-11-06 16:30:56 +090037
38/* ENV setting */
Nobuhiro Iwamatsuae870122014-11-06 16:30:56 +090039
40/* Common ENV setting */
41#define CONFIG_ENV_OVERWRITE
Nobuhiro Iwamatsuae870122014-11-06 16:30:56 +090042
Marek Vasutdc891972018-05-31 14:42:12 +020043/* SF MTD */
Frieder Schrempfd7be62c2019-10-23 07:41:20 +000044#ifdef CONFIG_SPL_BUILD
Marek Vasut20106932019-02-19 05:07:13 +010045#undef CONFIG_DM_SPI
46#undef CONFIG_DM_SPI_FLASH
Marek Vasutdc891972018-05-31 14:42:12 +020047#endif
48
Marek Vasut41316702018-08-24 21:52:53 +020049/* Timer */
50#define CONFIG_TMU_TIMER
51#define CONFIG_SYS_TIMER_COUNTS_DOWN
52#define CONFIG_SYS_TIMER_COUNTER (TMU_BASE + 0xc) /* TCNT0 */
Marek Vasut0b1bfa82018-09-19 16:33:09 +020053#define CONFIG_SYS_TIMER_RATE (CONFIG_SYS_CLK_FREQ / 8)
Marek Vasut41316702018-08-24 21:52:53 +020054
Nobuhiro Iwamatsuae870122014-11-06 16:30:56 +090055#endif /* __RCAR_GEN2_COMMON_H */