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Tom Rini10e47792018-05-06 17:58:06 -04001/* SPDX-License-Identifier: GPL-2.0+ */
Fabio Estevam77e62892012-09-13 03:18:20 +00002/*
3 * Copyright (C) 2012 Freescale Semiconductor, Inc.
4 *
5 * Configuration settings for the Freescale i.MX6Q SabreSD board.
Fabio Estevam77e62892012-09-13 03:18:20 +00006 */
7
Fabio Estevamc1239082017-06-01 12:59:52 -03008#ifndef __MX6SABRESD_CONFIG_H
9#define __MX6SABRESD_CONFIG_H
Fabio Estevam77e62892012-09-13 03:18:20 +000010
John Tobias7706eae2014-11-12 14:27:44 -080011#ifdef CONFIG_SPL
John Tobias7706eae2014-11-12 14:27:44 -080012#include "imx6_spl.h"
13#endif
14
Fabio Estevam77e62892012-09-13 03:18:20 +000015#define CONFIG_MACH_TYPE 3980
Fabio Estevamc5ca8972012-09-24 08:09:32 +000016#define CONFIG_MXC_UART_BASE UART1_BASE
Simon Glass4694a742016-10-17 20:12:39 -060017#define CONSOLE_DEV "ttymxc0"
Fabio Estevam77e62892012-09-13 03:18:20 +000018
Pierre Aubertec10aed2013-06-04 09:00:15 +020019#include "mx6sabre_common.h"
Otavio Salvador1c0b9be2012-09-26 11:37:01 +000020
Diego Dorta466016e2016-10-11 11:09:27 -030021/* Falcon Mode */
Tom Rini133b2e22017-01-20 19:55:53 -050022#define CONFIG_SPL_FS_LOAD_ARGS_NAME "args"
23#define CONFIG_SPL_FS_LOAD_KERNEL_NAME "uImage"
Diego Dorta466016e2016-10-11 11:09:27 -030024#define CONFIG_SYS_SPL_ARGS_ADDR 0x18000000
Diego Dorta466016e2016-10-11 11:09:27 -030025
26/* Falcon Mode - MMC support: args@1MB kernel@2MB */
27#define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTOR 0x800 /* 1MB */
28#define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTORS (CONFIG_CMD_SPL_WRITE_SIZE / 512)
29#define CONFIG_SYS_MMCSD_RAW_MODE_KERNEL_SECTOR 0x1000 /* 2MB */
30
Shawn Guo7e5e8332012-12-30 14:14:59 +000031#define CONFIG_SYS_FSL_USDHC_NUM 3
32#if defined(CONFIG_ENV_IS_IN_MMC)
Fabio Estevam3cce37d2013-01-10 09:00:53 +000033#define CONFIG_SYS_MMC_ENV_DEV 1 /* SDHC3 */
Shawn Guo7e5e8332012-12-30 14:14:59 +000034#endif
35
Marek Vasut0e99f012014-03-23 22:45:41 +010036#ifdef CONFIG_CMD_PCI
Marek Vasut0e99f012014-03-23 22:45:41 +010037#define CONFIG_PCI_SCAN_SHOW
38#define CONFIG_PCIE_IMX
39#define CONFIG_PCIE_IMX_PERST_GPIO IMX_GPIO_NR(7, 12)
40#define CONFIG_PCIE_IMX_POWER_GPIO IMX_GPIO_NR(3, 19)
41#endif
42
Fabio Estevamba92ad62014-05-09 13:15:42 -030043/* I2C Configs */
Fabio Estevamba92ad62014-05-09 13:15:42 -030044#define CONFIG_SYS_I2C
45#define CONFIG_SYS_I2C_MXC
Albert ARIBAUD \\(3ADEV\\)eb943872015-09-21 22:43:38 +020046#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */
47#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */
York Sunf1a52162015-03-20 10:20:40 -070048#define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */
Fabio Estevamba92ad62014-05-09 13:15:42 -030049#define CONFIG_SYS_I2C_SPEED 100000
50
51/* PMIC */
52#define CONFIG_POWER
53#define CONFIG_POWER_I2C
54#define CONFIG_POWER_PFUZE100
55#define CONFIG_POWER_PFUZE100_I2C_ADDR 0x08
56
Peng Fanc9498fa2014-12-02 09:55:27 +080057/* USB Configs */
Peng Fanc9498fa2014-12-02 09:55:27 +080058#ifdef CONFIG_CMD_USB
Peng Fanc9498fa2014-12-02 09:55:27 +080059#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
Peng Fanc9498fa2014-12-02 09:55:27 +080060#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW)
61#define CONFIG_MXC_USB_FLAGS 0
62#define CONFIG_USB_MAX_CONTROLLER_COUNT 1 /* Enabled USB controller number */
63#endif
64
Fabio Estevamccd298c2020-01-20 13:31:01 -030065#define CONFIG_FEC_MXC
66#define IMX_FEC_BASE ENET_BASE_ADDR
67#define CONFIG_FEC_XCV_TYPE RGMII
68#define CONFIG_ETHPRIME "FEC"
69#define CONFIG_FEC_MXC_PHYADDR 1
70
71#define CONFIG_PHY_ATHEROS
72
73
Fabio Estevamc1239082017-06-01 12:59:52 -030074#endif /* __MX6SABRESD_CONFIG_H */