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Tom Rini10e47792018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0+
Rick Chen36cb27c2017-12-26 13:55:53 +08002/*
3 * Copyright (C) 2017 Andes Technology Corporation
4 * Rick Chen, Andes Technology Corporation <rick@andestech.com>
Rick Chen36cb27c2017-12-26 13:55:53 +08005 */
6
Rick Chen36cb27c2017-12-26 13:55:53 +08007#include <common.h>
Simon Glass8e16b1e2019-12-28 10:45:05 -07008#include <init.h>
Rick Chen36cb27c2017-12-26 13:55:53 +08009#if defined(CONFIG_FTMAC100) && !defined(CONFIG_DM_ETH)
10#include <netdev.h>
11#endif
12#include <linux/io.h>
Rick Chencea16d02018-05-29 11:07:53 +080013#include <faraday/ftsmc020.h>
14#include <fdtdec.h>
Rick Chen9e017162019-08-28 18:46:07 +080015#include <dm.h>
Rick Chenc3027d02019-11-14 13:52:22 +080016#include <spl.h>
Rick Chen36cb27c2017-12-26 13:55:53 +080017
18DECLARE_GLOBAL_DATA_PTR;
19
Rick Chen2a218152018-12-03 17:48:20 +080020extern phys_addr_t prior_stage_fdt_address;
Rick Chen36cb27c2017-12-26 13:55:53 +080021/*
22 * Miscellaneous platform dependent initializations
23 */
24
25int board_init(void)
26{
Rick Chen36cb27c2017-12-26 13:55:53 +080027 gd->bd->bi_boot_params = PHYS_SDRAM_0 + 0x400;
28
29 return 0;
30}
31
32int dram_init(void)
33{
Rick Chen92038262019-11-14 13:52:23 +080034 return fdtdec_setup_mem_size_base();
Rick Chen36cb27c2017-12-26 13:55:53 +080035}
36
37int dram_init_banksize(void)
38{
Rick Chen92038262019-11-14 13:52:23 +080039 return fdtdec_setup_memory_banksize();
Rick Chen36cb27c2017-12-26 13:55:53 +080040}
41
42#if defined(CONFIG_FTMAC100) && !defined(CONFIG_DM_ETH)
43int board_eth_init(bd_t *bd)
44{
45 return ftmac100_initialize(bd);
46}
47#endif
48
49ulong board_flash_get_legacy(ulong base, int banknum, flash_info_t *info)
50{
51 return 0;
52}
Rick Chen40a6fe72018-03-29 10:08:33 +080053
54void *board_fdt_blob_setup(void)
55{
Rick Chen40a6fe72018-03-29 10:08:33 +080056 return (void *)CONFIG_SYS_FDT_BASE;
57}
Rick Chencea16d02018-05-29 11:07:53 +080058
59int smc_init(void)
60{
61 int node = -1;
62 const char *compat = "andestech,atfsmc020";
63 void *blob = (void *)gd->fdt_blob;
64 fdt_addr_t addr;
65 struct ftsmc020_bank *regs;
66
67 node = fdt_node_offset_by_compatible(blob, -1, compat);
68 if (node < 0)
69 return -FDT_ERR_NOTFOUND;
70
71 addr = fdtdec_get_addr(blob, node, "reg");
72
73 if (addr == FDT_ADDR_T_NONE)
74 return -EINVAL;
75
76 regs = (struct ftsmc020_bank *)addr;
77 regs->cr &= ~FTSMC020_BANK_WPROT;
78
79 return 0;
80}
81
Rick Chen9e017162019-08-28 18:46:07 +080082static void v5l2_init(void)
83{
84 struct udevice *dev;
85
86 uclass_get_device(UCLASS_CACHE, 0, &dev);
87}
88
Rick Chencea16d02018-05-29 11:07:53 +080089#ifdef CONFIG_BOARD_EARLY_INIT_F
90int board_early_init_f(void)
91{
92 smc_init();
Rick Chen9e017162019-08-28 18:46:07 +080093 v5l2_init();
Rick Chencea16d02018-05-29 11:07:53 +080094
95 return 0;
96}
97#endif
Rick Chenc3027d02019-11-14 13:52:22 +080098
99#ifdef CONFIG_SPL
100void board_boot_order(u32 *spl_boot_list)
101{
102 u8 i;
103 u32 boot_devices[] = {
104#ifdef CONFIG_SPL_RAM_SUPPORT
105 BOOT_DEVICE_RAM,
106#endif
107#ifdef CONFIG_SPL_MMC_SUPPORT
108 BOOT_DEVICE_MMC1,
109#endif
110 };
111
112 for (i = 0; i < ARRAY_SIZE(boot_devices); i++)
113 spl_boot_list[i] = boot_devices[i];
114}
115#endif
116
117#ifdef CONFIG_SPL_LOAD_FIT
118int board_fit_config_name_match(const char *name)
119{
120 /* boot using first FIT config */
121 return 0;
122}
123#endif