Chandan Nath | 7d74410 | 2011-10-14 02:58:26 +0000 | [diff] [blame] | 1 | /* |
| 2 | * mux.c |
| 3 | * |
| 4 | * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/ |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or |
| 7 | * modify it under the terms of the GNU General Public License as |
| 8 | * published by the Free Software Foundation version 2. |
| 9 | * |
| 10 | * This program is distributed "as is" WITHOUT ANY WARRANTY of any |
| 11 | * kind, whether express or implied; without even the implied warranty |
| 12 | * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 13 | * GNU General Public License for more details. |
| 14 | */ |
| 15 | |
Tom Rini | 7a24772 | 2012-07-31 10:50:01 -0700 | [diff] [blame] | 16 | #include <common.h> |
| 17 | #include <asm/arch/sys_proto.h> |
Chandan Nath | 7d74410 | 2011-10-14 02:58:26 +0000 | [diff] [blame] | 18 | #include <asm/arch/hardware.h> |
Peter Korsgaard | 5d3f682 | 2012-10-18 01:21:11 +0000 | [diff] [blame] | 19 | #include <asm/arch/mux.h> |
Chandan Nath | 7d74410 | 2011-10-14 02:58:26 +0000 | [diff] [blame] | 20 | #include <asm/io.h> |
Tom Rini | 184fffa | 2012-08-08 09:03:07 -0700 | [diff] [blame] | 21 | #include <i2c.h> |
Nishanth Menon | 2afa70d | 2016-02-24 12:30:55 -0600 | [diff] [blame] | 22 | #include "../common/board_detect.h" |
Peter Korsgaard | 85ec2db | 2012-10-18 01:21:09 +0000 | [diff] [blame] | 23 | #include "board.h" |
Chandan Nath | 7d74410 | 2011-10-14 02:58:26 +0000 | [diff] [blame] | 24 | |
Chandan Nath | 7d74410 | 2011-10-14 02:58:26 +0000 | [diff] [blame] | 25 | static struct module_pin_mux uart0_pin_mux[] = { |
| 26 | {OFFSET(uart0_rxd), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* UART0_RXD */ |
| 27 | {OFFSET(uart0_txd), (MODE(0) | PULLUDEN)}, /* UART0_TXD */ |
| 28 | {-1}, |
| 29 | }; |
| 30 | |
Andrew Bradford | 65c51ff | 2012-10-25 08:21:30 -0400 | [diff] [blame] | 31 | static struct module_pin_mux uart1_pin_mux[] = { |
| 32 | {OFFSET(uart1_rxd), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* UART1_RXD */ |
| 33 | {OFFSET(uart1_txd), (MODE(0) | PULLUDEN)}, /* UART1_TXD */ |
| 34 | {-1}, |
| 35 | }; |
| 36 | |
| 37 | static struct module_pin_mux uart2_pin_mux[] = { |
| 38 | {OFFSET(spi0_sclk), (MODE(1) | PULLUP_EN | RXACTIVE)}, /* UART2_RXD */ |
| 39 | {OFFSET(spi0_d0), (MODE(1) | PULLUDEN)}, /* UART2_TXD */ |
| 40 | {-1}, |
| 41 | }; |
| 42 | |
| 43 | static struct module_pin_mux uart3_pin_mux[] = { |
| 44 | {OFFSET(spi0_cs1), (MODE(1) | PULLUP_EN | RXACTIVE)}, /* UART3_RXD */ |
| 45 | {OFFSET(ecap0_in_pwm0_out), (MODE(1) | PULLUDEN)}, /* UART3_TXD */ |
| 46 | {-1}, |
| 47 | }; |
| 48 | |
| 49 | static struct module_pin_mux uart4_pin_mux[] = { |
| 50 | {OFFSET(gpmc_wait0), (MODE(6) | PULLUP_EN | RXACTIVE)}, /* UART4_RXD */ |
| 51 | {OFFSET(gpmc_wpn), (MODE(6) | PULLUDEN)}, /* UART4_TXD */ |
| 52 | {-1}, |
| 53 | }; |
| 54 | |
| 55 | static struct module_pin_mux uart5_pin_mux[] = { |
| 56 | {OFFSET(lcd_data9), (MODE(4) | PULLUP_EN | RXACTIVE)}, /* UART5_RXD */ |
| 57 | {OFFSET(lcd_data8), (MODE(4) | PULLUDEN)}, /* UART5_TXD */ |
| 58 | {-1}, |
| 59 | }; |
| 60 | |
Chandan Nath | d6e97f8 | 2012-01-09 20:38:58 +0000 | [diff] [blame] | 61 | static struct module_pin_mux mmc0_pin_mux[] = { |
| 62 | {OFFSET(mmc0_dat3), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT3 */ |
| 63 | {OFFSET(mmc0_dat2), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT2 */ |
| 64 | {OFFSET(mmc0_dat1), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT1 */ |
| 65 | {OFFSET(mmc0_dat0), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT0 */ |
| 66 | {OFFSET(mmc0_clk), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_CLK */ |
| 67 | {OFFSET(mmc0_cmd), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_CMD */ |
| 68 | {OFFSET(mcasp0_aclkr), (MODE(4) | RXACTIVE)}, /* MMC0_WP */ |
Mugunthan V N | 75bc003 | 2015-10-13 14:02:29 +0530 | [diff] [blame] | 69 | {OFFSET(spi0_cs1), (MODE(7) | RXACTIVE | PULLUP_EN)}, /* GPIO0_6 */ |
Chandan Nath | d6e97f8 | 2012-01-09 20:38:58 +0000 | [diff] [blame] | 70 | {-1}, |
| 71 | }; |
Tom Rini | 7a24772 | 2012-07-31 10:50:01 -0700 | [diff] [blame] | 72 | |
Matthias Fuchs | 63ffc5a | 2012-11-02 03:35:59 +0000 | [diff] [blame] | 73 | static struct module_pin_mux mmc0_no_cd_pin_mux[] = { |
| 74 | {OFFSET(mmc0_dat3), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT3 */ |
| 75 | {OFFSET(mmc0_dat2), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT2 */ |
| 76 | {OFFSET(mmc0_dat1), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT1 */ |
| 77 | {OFFSET(mmc0_dat0), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT0 */ |
| 78 | {OFFSET(mmc0_clk), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_CLK */ |
| 79 | {OFFSET(mmc0_cmd), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_CMD */ |
| 80 | {OFFSET(mcasp0_aclkr), (MODE(4) | RXACTIVE)}, /* MMC0_WP */ |
| 81 | {-1}, |
| 82 | }; |
| 83 | |
Tom Rini | 7a24772 | 2012-07-31 10:50:01 -0700 | [diff] [blame] | 84 | static struct module_pin_mux mmc0_pin_mux_sk_evm[] = { |
| 85 | {OFFSET(mmc0_dat3), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT3 */ |
| 86 | {OFFSET(mmc0_dat2), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT2 */ |
| 87 | {OFFSET(mmc0_dat1), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT1 */ |
| 88 | {OFFSET(mmc0_dat0), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT0 */ |
| 89 | {OFFSET(mmc0_clk), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_CLK */ |
| 90 | {OFFSET(mmc0_cmd), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_CMD */ |
| 91 | {OFFSET(spi0_cs1), (MODE(5) | RXACTIVE | PULLUP_EN)}, /* MMC0_CD */ |
| 92 | {-1}, |
| 93 | }; |
Chandan Nath | d6e97f8 | 2012-01-09 20:38:58 +0000 | [diff] [blame] | 94 | |
Tom Rini | 9670a1e | 2012-08-08 10:32:09 -0700 | [diff] [blame] | 95 | static struct module_pin_mux mmc1_pin_mux[] = { |
Jean-Jacques Hiblot | c1932e4 | 2019-05-23 14:07:23 +0200 | [diff] [blame] | 96 | {OFFSET(gpmc_ad7), (MODE(1) | RXACTIVE | PULLUP_EN)}, /* MMC1_DAT7 */ |
| 97 | {OFFSET(gpmc_ad6), (MODE(1) | RXACTIVE | PULLUP_EN)}, /* MMC1_DAT6 */ |
| 98 | {OFFSET(gpmc_ad5), (MODE(1) | RXACTIVE | PULLUP_EN)}, /* MMC1_DAT5 */ |
| 99 | {OFFSET(gpmc_ad4), (MODE(1) | RXACTIVE | PULLUP_EN)}, /* MMC1_DAT4 */ |
Tom Rini | 9670a1e | 2012-08-08 10:32:09 -0700 | [diff] [blame] | 100 | {OFFSET(gpmc_ad3), (MODE(1) | RXACTIVE | PULLUP_EN)}, /* MMC1_DAT3 */ |
| 101 | {OFFSET(gpmc_ad2), (MODE(1) | RXACTIVE | PULLUP_EN)}, /* MMC1_DAT2 */ |
| 102 | {OFFSET(gpmc_ad1), (MODE(1) | RXACTIVE | PULLUP_EN)}, /* MMC1_DAT1 */ |
| 103 | {OFFSET(gpmc_ad0), (MODE(1) | RXACTIVE | PULLUP_EN)}, /* MMC1_DAT0 */ |
| 104 | {OFFSET(gpmc_csn1), (MODE(2) | RXACTIVE | PULLUP_EN)}, /* MMC1_CLK */ |
| 105 | {OFFSET(gpmc_csn2), (MODE(2) | RXACTIVE | PULLUP_EN)}, /* MMC1_CMD */ |
| 106 | {OFFSET(gpmc_csn0), (MODE(7) | RXACTIVE | PULLUP_EN)}, /* MMC1_WP */ |
| 107 | {OFFSET(gpmc_advn_ale), (MODE(7) | RXACTIVE | PULLUP_EN)}, /* MMC1_CD */ |
| 108 | {-1}, |
| 109 | }; |
| 110 | |
Patil, Rachna | 5f70c51 | 2012-01-22 23:47:01 +0000 | [diff] [blame] | 111 | static struct module_pin_mux i2c0_pin_mux[] = { |
| 112 | {OFFSET(i2c0_sda), (MODE(0) | RXACTIVE | |
| 113 | PULLUDEN | SLEWCTRL)}, /* I2C_DATA */ |
| 114 | {OFFSET(i2c0_scl), (MODE(0) | RXACTIVE | |
| 115 | PULLUDEN | SLEWCTRL)}, /* I2C_SCLK */ |
| 116 | {-1}, |
| 117 | }; |
| 118 | |
Steve Sakoman | 695b1fe | 2012-06-22 07:45:57 +0000 | [diff] [blame] | 119 | static struct module_pin_mux i2c1_pin_mux[] = { |
| 120 | {OFFSET(spi0_d1), (MODE(2) | RXACTIVE | |
| 121 | PULLUDEN | SLEWCTRL)}, /* I2C_DATA */ |
| 122 | {OFFSET(spi0_cs0), (MODE(2) | RXACTIVE | |
| 123 | PULLUDEN | SLEWCTRL)}, /* I2C_SCLK */ |
| 124 | {-1}, |
| 125 | }; |
| 126 | |
Kory Maincent | 4c1a71d | 2021-05-04 19:31:29 +0200 | [diff] [blame] | 127 | static struct module_pin_mux i2c2_pin_mux[] = { |
| 128 | {OFFSET(uart1_ctsn), (MODE(3) | RXACTIVE | |
| 129 | PULLUDEN | PULLUP_EN | SLEWCTRL)}, /* I2C_DATA */ |
| 130 | {OFFSET(uart1_rtsn), (MODE(3) | RXACTIVE | |
| 131 | PULLUDEN | PULLUP_EN | SLEWCTRL)}, /* I2C_SCLK */ |
| 132 | {-1}, |
| 133 | }; |
| 134 | |
Tom Rini | 883401e | 2012-08-08 14:35:55 -0700 | [diff] [blame] | 135 | static struct module_pin_mux spi0_pin_mux[] = { |
| 136 | {OFFSET(spi0_sclk), (MODE(0) | RXACTIVE | PULLUDEN)}, /* SPI0_SCLK */ |
| 137 | {OFFSET(spi0_d0), (MODE(0) | RXACTIVE | |
| 138 | PULLUDEN | PULLUP_EN)}, /* SPI0_D0 */ |
| 139 | {OFFSET(spi0_d1), (MODE(0) | RXACTIVE | PULLUDEN)}, /* SPI0_D1 */ |
| 140 | {OFFSET(spi0_cs0), (MODE(0) | RXACTIVE | |
| 141 | PULLUDEN | PULLUP_EN)}, /* SPI0_CS0 */ |
| 142 | {-1}, |
| 143 | }; |
| 144 | |
Tom Rini | 4b30240 | 2012-07-31 08:55:01 -0700 | [diff] [blame] | 145 | static struct module_pin_mux gpio0_7_pin_mux[] = { |
| 146 | {OFFSET(ecap0_in_pwm0_out), (MODE(7) | PULLUDEN)}, /* GPIO0_7 */ |
| 147 | {-1}, |
| 148 | }; |
| 149 | |
Lokesh Vutla | 3112ea2 | 2016-05-16 11:47:23 +0530 | [diff] [blame] | 150 | static struct module_pin_mux gpio0_18_pin_mux[] = { |
| 151 | {OFFSET(usb0_drvvbus), (MODE(7) | PULLUDEN)}, /* GPIO0_18 */ |
| 152 | {-1}, |
| 153 | }; |
| 154 | |
Chandan Nath | b79a12e | 2012-07-24 12:22:18 +0000 | [diff] [blame] | 155 | static struct module_pin_mux rgmii1_pin_mux[] = { |
| 156 | {OFFSET(mii1_txen), MODE(2)}, /* RGMII1_TCTL */ |
| 157 | {OFFSET(mii1_rxdv), MODE(2) | RXACTIVE}, /* RGMII1_RCTL */ |
| 158 | {OFFSET(mii1_txd3), MODE(2)}, /* RGMII1_TD3 */ |
| 159 | {OFFSET(mii1_txd2), MODE(2)}, /* RGMII1_TD2 */ |
| 160 | {OFFSET(mii1_txd1), MODE(2)}, /* RGMII1_TD1 */ |
| 161 | {OFFSET(mii1_txd0), MODE(2)}, /* RGMII1_TD0 */ |
| 162 | {OFFSET(mii1_txclk), MODE(2)}, /* RGMII1_TCLK */ |
| 163 | {OFFSET(mii1_rxclk), MODE(2) | RXACTIVE}, /* RGMII1_RCLK */ |
| 164 | {OFFSET(mii1_rxd3), MODE(2) | RXACTIVE}, /* RGMII1_RD3 */ |
| 165 | {OFFSET(mii1_rxd2), MODE(2) | RXACTIVE}, /* RGMII1_RD2 */ |
| 166 | {OFFSET(mii1_rxd1), MODE(2) | RXACTIVE}, /* RGMII1_RD1 */ |
| 167 | {OFFSET(mii1_rxd0), MODE(2) | RXACTIVE}, /* RGMII1_RD0 */ |
| 168 | {OFFSET(mdio_data), MODE(0) | RXACTIVE | PULLUP_EN},/* MDIO_DATA */ |
| 169 | {OFFSET(mdio_clk), MODE(0) | PULLUP_EN}, /* MDIO_CLK */ |
| 170 | {-1}, |
| 171 | }; |
| 172 | |
| 173 | static struct module_pin_mux mii1_pin_mux[] = { |
| 174 | {OFFSET(mii1_rxerr), MODE(0) | RXACTIVE}, /* MII1_RXERR */ |
| 175 | {OFFSET(mii1_txen), MODE(0)}, /* MII1_TXEN */ |
| 176 | {OFFSET(mii1_rxdv), MODE(0) | RXACTIVE}, /* MII1_RXDV */ |
| 177 | {OFFSET(mii1_txd3), MODE(0)}, /* MII1_TXD3 */ |
| 178 | {OFFSET(mii1_txd2), MODE(0)}, /* MII1_TXD2 */ |
| 179 | {OFFSET(mii1_txd1), MODE(0)}, /* MII1_TXD1 */ |
| 180 | {OFFSET(mii1_txd0), MODE(0)}, /* MII1_TXD0 */ |
| 181 | {OFFSET(mii1_txclk), MODE(0) | RXACTIVE}, /* MII1_TXCLK */ |
| 182 | {OFFSET(mii1_rxclk), MODE(0) | RXACTIVE}, /* MII1_RXCLK */ |
| 183 | {OFFSET(mii1_rxd3), MODE(0) | RXACTIVE}, /* MII1_RXD3 */ |
| 184 | {OFFSET(mii1_rxd2), MODE(0) | RXACTIVE}, /* MII1_RXD2 */ |
| 185 | {OFFSET(mii1_rxd1), MODE(0) | RXACTIVE}, /* MII1_RXD1 */ |
| 186 | {OFFSET(mii1_rxd0), MODE(0) | RXACTIVE}, /* MII1_RXD0 */ |
| 187 | {OFFSET(mdio_data), MODE(0) | RXACTIVE | PULLUP_EN}, /* MDIO_DATA */ |
| 188 | {OFFSET(mdio_clk), MODE(0) | PULLUP_EN}, /* MDIO_CLK */ |
Lokesh Vutla | 3112ea2 | 2016-05-16 11:47:23 +0530 | [diff] [blame] | 189 | {-1}, |
| 190 | }; |
| 191 | |
| 192 | static struct module_pin_mux rmii1_pin_mux[] = { |
| 193 | {OFFSET(mdio_clk), MODE(0) | PULLUP_EN}, /* MDIO_CLK */ |
| 194 | {OFFSET(mdio_data), MODE(0) | RXACTIVE | PULLUP_EN}, /* MDIO_DATA */ |
| 195 | {OFFSET(mii1_crs), MODE(1) | RXACTIVE}, /* MII1_CRS */ |
| 196 | {OFFSET(mii1_rxerr), MODE(1) | RXACTIVE}, /* MII1_RXERR */ |
| 197 | {OFFSET(mii1_txen), MODE(1)}, /* MII1_TXEN */ |
| 198 | {OFFSET(mii1_txd1), MODE(1)}, /* MII1_TXD1 */ |
| 199 | {OFFSET(mii1_txd0), MODE(1)}, /* MII1_TXD0 */ |
| 200 | {OFFSET(mii1_rxd1), MODE(1) | RXACTIVE}, /* MII1_RXD1 */ |
| 201 | {OFFSET(mii1_rxd0), MODE(1) | RXACTIVE}, /* MII1_RXD0 */ |
| 202 | {OFFSET(rmii1_refclk), MODE(0) | RXACTIVE}, /* RMII1_REFCLK */ |
Chandan Nath | b79a12e | 2012-07-24 12:22:18 +0000 | [diff] [blame] | 203 | {-1}, |
| 204 | }; |
| 205 | |
Miquel Raynal | d093536 | 2019-10-03 19:50:03 +0200 | [diff] [blame] | 206 | #ifdef CONFIG_MTD_RAW_NAND |
Ilya Yanok | fd05655 | 2012-11-06 13:06:29 +0000 | [diff] [blame] | 207 | static struct module_pin_mux nand_pin_mux[] = { |
pekon gupta | 2badbde | 2014-07-22 16:03:20 +0530 | [diff] [blame] | 208 | {OFFSET(gpmc_ad0), (MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD0 */ |
| 209 | {OFFSET(gpmc_ad1), (MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD1 */ |
| 210 | {OFFSET(gpmc_ad2), (MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD2 */ |
| 211 | {OFFSET(gpmc_ad3), (MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD3 */ |
| 212 | {OFFSET(gpmc_ad4), (MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD4 */ |
| 213 | {OFFSET(gpmc_ad5), (MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD5 */ |
| 214 | {OFFSET(gpmc_ad6), (MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD6 */ |
| 215 | {OFFSET(gpmc_ad7), (MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD7 */ |
| 216 | #ifdef CONFIG_SYS_NAND_BUSWIDTH_16BIT |
| 217 | {OFFSET(gpmc_ad8), (MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD8 */ |
| 218 | {OFFSET(gpmc_ad9), (MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD9 */ |
| 219 | {OFFSET(gpmc_ad10), (MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD10 */ |
| 220 | {OFFSET(gpmc_ad11), (MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD11 */ |
| 221 | {OFFSET(gpmc_ad12), (MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD12 */ |
| 222 | {OFFSET(gpmc_ad13), (MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD13 */ |
| 223 | {OFFSET(gpmc_ad14), (MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD14 */ |
| 224 | {OFFSET(gpmc_ad15), (MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD15 */ |
| 225 | #endif |
| 226 | {OFFSET(gpmc_wait0), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* nWAIT */ |
| 227 | {OFFSET(gpmc_wpn), (MODE(7) | PULLUP_EN)}, /* nWP */ |
| 228 | {OFFSET(gpmc_csn0), (MODE(0) | PULLUP_EN)}, /* nCS */ |
| 229 | {OFFSET(gpmc_wen), (MODE(0) | PULLDOWN_EN)}, /* WEN */ |
| 230 | {OFFSET(gpmc_oen_ren), (MODE(0) | PULLDOWN_EN)}, /* OE */ |
| 231 | {OFFSET(gpmc_advn_ale), (MODE(0) | PULLDOWN_EN)}, /* ADV_ALE */ |
| 232 | {OFFSET(gpmc_be0n_cle), (MODE(0) | PULLDOWN_EN)}, /* BE_CLE */ |
Ilya Yanok | fd05655 | 2012-11-06 13:06:29 +0000 | [diff] [blame] | 233 | {-1}, |
| 234 | }; |
pekon gupta | 0efbdcf | 2014-07-22 16:03:21 +0530 | [diff] [blame] | 235 | #elif defined(CONFIG_NOR) |
Steve Kipisz | be9b6f8 | 2013-07-18 15:13:03 -0400 | [diff] [blame] | 236 | static struct module_pin_mux bone_norcape_pin_mux[] = { |
pekon gupta | 0efbdcf | 2014-07-22 16:03:21 +0530 | [diff] [blame] | 237 | {OFFSET(gpmc_a0), MODE(0) | PULLUDDIS}, /* NOR_A0 */ |
| 238 | {OFFSET(gpmc_a1), MODE(0) | PULLUDDIS}, /* NOR_A1 */ |
| 239 | {OFFSET(gpmc_a2), MODE(0) | PULLUDDIS}, /* NOR_A2 */ |
| 240 | {OFFSET(gpmc_a3), MODE(0) | PULLUDDIS}, /* NOR_A3 */ |
| 241 | {OFFSET(gpmc_a4), MODE(0) | PULLUDDIS}, /* NOR_A4 */ |
| 242 | {OFFSET(gpmc_a5), MODE(0) | PULLUDDIS}, /* NOR_A5 */ |
| 243 | {OFFSET(gpmc_a6), MODE(0) | PULLUDDIS}, /* NOR_A6 */ |
| 244 | {OFFSET(gpmc_a7), MODE(0) | PULLUDDIS}, /* NOR_A7 */ |
| 245 | {OFFSET(gpmc_ad0), MODE(0) | PULLUDDIS | RXACTIVE}, /* NOR_AD0 */ |
| 246 | {OFFSET(gpmc_ad1), MODE(0) | PULLUDDIS | RXACTIVE}, /* NOR_AD1 */ |
| 247 | {OFFSET(gpmc_ad2), MODE(0) | PULLUDDIS | RXACTIVE}, /* NOR_AD2 */ |
| 248 | {OFFSET(gpmc_ad3), MODE(0) | PULLUDDIS | RXACTIVE}, /* NOR_AD3 */ |
| 249 | {OFFSET(gpmc_ad4), MODE(0) | PULLUDDIS | RXACTIVE}, /* NOR_AD4 */ |
| 250 | {OFFSET(gpmc_ad5), MODE(0) | PULLUDDIS | RXACTIVE}, /* NOR_AD5 */ |
| 251 | {OFFSET(gpmc_ad6), MODE(0) | PULLUDDIS | RXACTIVE}, /* NOR_AD6 */ |
| 252 | {OFFSET(gpmc_ad7), MODE(0) | PULLUDDIS | RXACTIVE}, /* NOR_AD7 */ |
| 253 | {OFFSET(gpmc_ad8), MODE(0) | PULLUDDIS | RXACTIVE}, /* NOR_AD8 */ |
| 254 | {OFFSET(gpmc_ad9), MODE(0) | PULLUDDIS | RXACTIVE}, /* NOR_AD9 */ |
| 255 | {OFFSET(gpmc_ad10), MODE(0) | PULLUDDIS | RXACTIVE}, /* NOR_AD10 */ |
| 256 | {OFFSET(gpmc_ad11), MODE(0) | PULLUDDIS | RXACTIVE}, /* NOR_AD11 */ |
| 257 | {OFFSET(gpmc_ad12), MODE(0) | PULLUDDIS | RXACTIVE}, /* NOR_AD12 */ |
| 258 | {OFFSET(gpmc_ad13), MODE(0) | PULLUDDIS | RXACTIVE}, /* NOR_AD13 */ |
| 259 | {OFFSET(gpmc_ad14), MODE(0) | PULLUDDIS | RXACTIVE}, /* NOR_AD14 */ |
| 260 | {OFFSET(gpmc_ad15), MODE(0) | PULLUDDIS | RXACTIVE}, /* NOR_AD15 */ |
| 261 | {OFFSET(gpmc_csn0), MODE(0) | PULLUDEN | PULLUP_EN}, /* CE */ |
| 262 | {OFFSET(gpmc_advn_ale), MODE(0) | PULLUDEN | PULLDOWN_EN}, /* ALE */ |
| 263 | {OFFSET(gpmc_oen_ren), MODE(0) | PULLUDEN | PULLDOWN_EN},/* OEn_REN */ |
| 264 | {OFFSET(gpmc_be0n_cle), MODE(0) | PULLUDEN | PULLDOWN_EN},/* unused */ |
| 265 | {OFFSET(gpmc_wen), MODE(0) | PULLUDEN | PULLDOWN_EN}, /* WEN */ |
| 266 | {OFFSET(gpmc_wait0), MODE(0) | PULLUDEN | PULLUP_EN | RXACTIVE},/*WAIT*/ |
Steve Kipisz | be9b6f8 | 2013-07-18 15:13:03 -0400 | [diff] [blame] | 267 | {-1}, |
| 268 | }; |
| 269 | #endif |
| 270 | |
Lokesh Vutla | 3112ea2 | 2016-05-16 11:47:23 +0530 | [diff] [blame] | 271 | static struct module_pin_mux uart3_icev2_pin_mux[] = { |
| 272 | {OFFSET(mii1_rxd3), (MODE(1) | PULLUP_EN | RXACTIVE)}, /* UART3_RXD */ |
| 273 | {OFFSET(mii1_rxd2), MODE(1) | PULLUDEN}, /* UART3_TXD */ |
| 274 | {-1}, |
| 275 | }; |
| 276 | |
Heiko Schocher | b21f2ac | 2013-07-30 10:48:54 +0530 | [diff] [blame] | 277 | #if defined(CONFIG_NOR_BOOT) |
Heiko Schocher | b21f2ac | 2013-07-30 10:48:54 +0530 | [diff] [blame] | 278 | void enable_norboot_pin_mux(void) |
| 279 | { |
pekon gupta | 0efbdcf | 2014-07-22 16:03:21 +0530 | [diff] [blame] | 280 | configure_module_pin_mux(bone_norcape_pin_mux); |
Heiko Schocher | b21f2ac | 2013-07-30 10:48:54 +0530 | [diff] [blame] | 281 | } |
| 282 | #endif |
Steve Kipisz | be9b6f8 | 2013-07-18 15:13:03 -0400 | [diff] [blame] | 283 | |
Chandan Nath | 7d74410 | 2011-10-14 02:58:26 +0000 | [diff] [blame] | 284 | void enable_uart0_pin_mux(void) |
| 285 | { |
| 286 | configure_module_pin_mux(uart0_pin_mux); |
| 287 | } |
Chandan Nath | d6e97f8 | 2012-01-09 20:38:58 +0000 | [diff] [blame] | 288 | |
Andrew Bradford | 65c51ff | 2012-10-25 08:21:30 -0400 | [diff] [blame] | 289 | void enable_uart1_pin_mux(void) |
| 290 | { |
| 291 | configure_module_pin_mux(uart1_pin_mux); |
| 292 | } |
| 293 | |
| 294 | void enable_uart2_pin_mux(void) |
| 295 | { |
| 296 | configure_module_pin_mux(uart2_pin_mux); |
| 297 | } |
| 298 | |
| 299 | void enable_uart3_pin_mux(void) |
| 300 | { |
| 301 | configure_module_pin_mux(uart3_pin_mux); |
| 302 | } |
| 303 | |
| 304 | void enable_uart4_pin_mux(void) |
| 305 | { |
| 306 | configure_module_pin_mux(uart4_pin_mux); |
| 307 | } |
| 308 | |
| 309 | void enable_uart5_pin_mux(void) |
| 310 | { |
| 311 | configure_module_pin_mux(uart5_pin_mux); |
| 312 | } |
Patil, Rachna | 5f70c51 | 2012-01-22 23:47:01 +0000 | [diff] [blame] | 313 | |
| 314 | void enable_i2c0_pin_mux(void) |
| 315 | { |
| 316 | configure_module_pin_mux(i2c0_pin_mux); |
| 317 | } |
Steve Sakoman | 695b1fe | 2012-06-22 07:45:57 +0000 | [diff] [blame] | 318 | |
Kory Maincent | 4c1a71d | 2021-05-04 19:31:29 +0200 | [diff] [blame] | 319 | void enable_i2c2_pin_mux(void) |
| 320 | { |
| 321 | configure_module_pin_mux(i2c2_pin_mux); |
| 322 | } |
| 323 | |
Tom Rini | 184fffa | 2012-08-08 09:03:07 -0700 | [diff] [blame] | 324 | /* |
| 325 | * The AM335x GP EVM, if daughter card(s) are connected, can have 8 |
| 326 | * different profiles. These profiles determine what peripherals are |
| 327 | * valid and need pinmux to be configured. |
| 328 | */ |
| 329 | #define PROFILE_NONE 0x0 |
| 330 | #define PROFILE_0 (1 << 0) |
| 331 | #define PROFILE_1 (1 << 1) |
| 332 | #define PROFILE_2 (1 << 2) |
| 333 | #define PROFILE_3 (1 << 3) |
| 334 | #define PROFILE_4 (1 << 4) |
| 335 | #define PROFILE_5 (1 << 5) |
| 336 | #define PROFILE_6 (1 << 6) |
| 337 | #define PROFILE_7 (1 << 7) |
| 338 | #define PROFILE_MASK 0x7 |
| 339 | #define PROFILE_ALL 0xFF |
| 340 | |
| 341 | /* CPLD registers */ |
| 342 | #define I2C_CPLD_ADDR 0x35 |
| 343 | #define CFG_REG 0x10 |
| 344 | |
| 345 | static unsigned short detect_daughter_board_profile(void) |
Steve Sakoman | 695b1fe | 2012-06-22 07:45:57 +0000 | [diff] [blame] | 346 | { |
Tom Rini | 184fffa | 2012-08-08 09:03:07 -0700 | [diff] [blame] | 347 | unsigned short val; |
Chandan Nath | b79a12e | 2012-07-24 12:22:18 +0000 | [diff] [blame] | 348 | |
Igor Opaniuk | f7c9176 | 2021-02-09 13:52:45 +0200 | [diff] [blame] | 349 | #if !CONFIG_IS_ENABLED(DM_I2C) |
Tom Rini | 184fffa | 2012-08-08 09:03:07 -0700 | [diff] [blame] | 350 | if (i2c_probe(I2C_CPLD_ADDR)) |
| 351 | return PROFILE_NONE; |
| 352 | |
| 353 | if (i2c_read(I2C_CPLD_ADDR, CFG_REG, 1, (unsigned char *)(&val), 2)) |
| 354 | return PROFILE_NONE; |
Jean-Jacques Hiblot | 52a5151 | 2018-12-07 14:50:49 +0100 | [diff] [blame] | 355 | #else |
| 356 | struct udevice *dev = NULL; |
| 357 | int rc; |
Tom Rini | 184fffa | 2012-08-08 09:03:07 -0700 | [diff] [blame] | 358 | |
Jean-Jacques Hiblot | 52a5151 | 2018-12-07 14:50:49 +0100 | [diff] [blame] | 359 | rc = i2c_get_chip_for_busnum(0, I2C_CPLD_ADDR, 1, &dev); |
| 360 | if (rc) |
| 361 | return PROFILE_NONE; |
| 362 | rc = dm_i2c_read(dev, CFG_REG, (unsigned char *)(&val), 2); |
| 363 | if (rc) |
| 364 | return PROFILE_NONE; |
| 365 | #endif |
Tom Rini | 184fffa | 2012-08-08 09:03:07 -0700 | [diff] [blame] | 366 | return (1 << (val & PROFILE_MASK)); |
| 367 | } |
| 368 | |
Nishanth Menon | 2afa70d | 2016-02-24 12:30:55 -0600 | [diff] [blame] | 369 | void enable_board_pin_mux(void) |
Tom Rini | 184fffa | 2012-08-08 09:03:07 -0700 | [diff] [blame] | 370 | { |
| 371 | /* Do board-specific muxes. */ |
Nishanth Menon | 2afa70d | 2016-02-24 12:30:55 -0600 | [diff] [blame] | 372 | if (board_is_bone()) { |
Tom Rini | 7a24772 | 2012-07-31 10:50:01 -0700 | [diff] [blame] | 373 | /* Beaglebone pinmux */ |
| 374 | configure_module_pin_mux(mii1_pin_mux); |
| 375 | configure_module_pin_mux(mmc0_pin_mux); |
Miquel Raynal | d093536 | 2019-10-03 19:50:03 +0200 | [diff] [blame] | 376 | #if defined(CONFIG_MTD_RAW_NAND) |
pekon gupta | 2badbde | 2014-07-22 16:03:20 +0530 | [diff] [blame] | 377 | configure_module_pin_mux(nand_pin_mux); |
pekon gupta | 0efbdcf | 2014-07-22 16:03:21 +0530 | [diff] [blame] | 378 | #elif defined(CONFIG_NOR) |
Steve Kipisz | be9b6f8 | 2013-07-18 15:13:03 -0400 | [diff] [blame] | 379 | configure_module_pin_mux(bone_norcape_pin_mux); |
pekon gupta | 2badbde | 2014-07-22 16:03:20 +0530 | [diff] [blame] | 380 | #else |
| 381 | configure_module_pin_mux(mmc1_pin_mux); |
Steve Kipisz | be9b6f8 | 2013-07-18 15:13:03 -0400 | [diff] [blame] | 382 | #endif |
Kory Maincent | 4c1a71d | 2021-05-04 19:31:29 +0200 | [diff] [blame] | 383 | configure_module_pin_mux(i2c2_pin_mux); |
Nishanth Menon | 2afa70d | 2016-02-24 12:30:55 -0600 | [diff] [blame] | 384 | } else if (board_is_gp_evm()) { |
Tom Rini | 7a24772 | 2012-07-31 10:50:01 -0700 | [diff] [blame] | 385 | /* General Purpose EVM */ |
Tom Rini | 184fffa | 2012-08-08 09:03:07 -0700 | [diff] [blame] | 386 | unsigned short profile = detect_daughter_board_profile(); |
Tom Rini | 7a24772 | 2012-07-31 10:50:01 -0700 | [diff] [blame] | 387 | configure_module_pin_mux(rgmii1_pin_mux); |
| 388 | configure_module_pin_mux(mmc0_pin_mux); |
Tom Rini | 184fffa | 2012-08-08 09:03:07 -0700 | [diff] [blame] | 389 | /* In profile #2 i2c1 and spi0 conflict. */ |
| 390 | if (profile & ~PROFILE_2) |
| 391 | configure_module_pin_mux(i2c1_pin_mux); |
Ilya Yanok | fd05655 | 2012-11-06 13:06:29 +0000 | [diff] [blame] | 392 | /* Profiles 2 & 3 don't have NAND */ |
Miquel Raynal | d093536 | 2019-10-03 19:50:03 +0200 | [diff] [blame] | 393 | #ifdef CONFIG_MTD_RAW_NAND |
Ilya Yanok | fd05655 | 2012-11-06 13:06:29 +0000 | [diff] [blame] | 394 | if (profile & ~(PROFILE_2 | PROFILE_3)) |
| 395 | configure_module_pin_mux(nand_pin_mux); |
pekon gupta | 2badbde | 2014-07-22 16:03:20 +0530 | [diff] [blame] | 396 | #endif |
Tom Rini | 9670a1e | 2012-08-08 10:32:09 -0700 | [diff] [blame] | 397 | else if (profile == PROFILE_2) { |
| 398 | configure_module_pin_mux(mmc1_pin_mux); |
Tom Rini | 883401e | 2012-08-08 14:35:55 -0700 | [diff] [blame] | 399 | configure_module_pin_mux(spi0_pin_mux); |
Tom Rini | 9670a1e | 2012-08-08 10:32:09 -0700 | [diff] [blame] | 400 | } |
Nishanth Menon | 2afa70d | 2016-02-24 12:30:55 -0600 | [diff] [blame] | 401 | } else if (board_is_idk()) { |
Tom Rini | 986d755 | 2014-08-01 09:53:24 -0400 | [diff] [blame] | 402 | /* Industrial Motor Control (IDK) */ |
Matthias Fuchs | 63ffc5a | 2012-11-02 03:35:59 +0000 | [diff] [blame] | 403 | configure_module_pin_mux(mii1_pin_mux); |
| 404 | configure_module_pin_mux(mmc0_no_cd_pin_mux); |
Nishanth Menon | 2afa70d | 2016-02-24 12:30:55 -0600 | [diff] [blame] | 405 | } else if (board_is_evm_sk()) { |
Tom Rini | 7a24772 | 2012-07-31 10:50:01 -0700 | [diff] [blame] | 406 | /* Starter Kit EVM */ |
Tom Rini | 184fffa | 2012-08-08 09:03:07 -0700 | [diff] [blame] | 407 | configure_module_pin_mux(i2c1_pin_mux); |
Tom Rini | 7a24772 | 2012-07-31 10:50:01 -0700 | [diff] [blame] | 408 | configure_module_pin_mux(gpio0_7_pin_mux); |
| 409 | configure_module_pin_mux(rgmii1_pin_mux); |
| 410 | configure_module_pin_mux(mmc0_pin_mux_sk_evm); |
Nishanth Menon | 2afa70d | 2016-02-24 12:30:55 -0600 | [diff] [blame] | 411 | } else if (board_is_bone_lt()) { |
Koen Kooi | 8a15786 | 2018-07-18 10:13:59 +0200 | [diff] [blame] | 412 | if (board_is_bben()) { |
| 413 | /* SanCloud Beaglebone LT Enhanced pinmux */ |
| 414 | configure_module_pin_mux(rgmii1_pin_mux); |
| 415 | } else { |
| 416 | /* Beaglebone LT pinmux */ |
| 417 | configure_module_pin_mux(mii1_pin_mux); |
| 418 | } |
Koen Kooi | 95e7947 | 2012-10-23 01:56:40 +0000 | [diff] [blame] | 419 | /* Beaglebone LT pinmux */ |
Koen Kooi | 95e7947 | 2012-10-23 01:56:40 +0000 | [diff] [blame] | 420 | configure_module_pin_mux(mmc0_pin_mux); |
Miquel Raynal | d093536 | 2019-10-03 19:50:03 +0200 | [diff] [blame] | 421 | #if defined(CONFIG_MTD_RAW_NAND) && defined(CONFIG_EMMC_BOOT) |
pekon gupta | 2badbde | 2014-07-22 16:03:20 +0530 | [diff] [blame] | 422 | configure_module_pin_mux(nand_pin_mux); |
Tom Rini | ef4c481 | 2014-10-08 17:10:27 -0400 | [diff] [blame] | 423 | #elif defined(CONFIG_NOR) && defined(CONFIG_EMMC_BOOT) |
pekon gupta | 0efbdcf | 2014-07-22 16:03:21 +0530 | [diff] [blame] | 424 | configure_module_pin_mux(bone_norcape_pin_mux); |
pekon gupta | 2badbde | 2014-07-22 16:03:20 +0530 | [diff] [blame] | 425 | #else |
Koen Kooi | 95e7947 | 2012-10-23 01:56:40 +0000 | [diff] [blame] | 426 | configure_module_pin_mux(mmc1_pin_mux); |
pekon gupta | 2badbde | 2014-07-22 16:03:20 +0530 | [diff] [blame] | 427 | #endif |
Kory Maincent | 4c1a71d | 2021-05-04 19:31:29 +0200 | [diff] [blame] | 428 | configure_module_pin_mux(i2c2_pin_mux); |
Jason Kridner | b56b5b3 | 2018-03-07 05:40:41 -0500 | [diff] [blame] | 429 | } else if (board_is_pb()) { |
| 430 | configure_module_pin_mux(mii1_pin_mux); |
| 431 | configure_module_pin_mux(mmc0_pin_mux); |
Lokesh Vutla | 3112ea2 | 2016-05-16 11:47:23 +0530 | [diff] [blame] | 432 | } else if (board_is_icev2()) { |
| 433 | configure_module_pin_mux(mmc0_pin_mux); |
| 434 | configure_module_pin_mux(gpio0_18_pin_mux); |
| 435 | configure_module_pin_mux(uart3_icev2_pin_mux); |
| 436 | configure_module_pin_mux(rmii1_pin_mux); |
| 437 | configure_module_pin_mux(spi0_pin_mux); |
Tom Rini | 7a24772 | 2012-07-31 10:50:01 -0700 | [diff] [blame] | 438 | } else { |
Alex G | 7c195e6 | 2016-11-08 20:48:44 -0800 | [diff] [blame] | 439 | /* Unknown board. We might still be able to boot. */ |
| 440 | puts("Bad EEPROM or unknown board, cannot configure pinmux."); |
Tom Rini | 7a24772 | 2012-07-31 10:50:01 -0700 | [diff] [blame] | 441 | } |
Tom Rini | 4b30240 | 2012-07-31 08:55:01 -0700 | [diff] [blame] | 442 | } |