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Yusuke Godacf236022008-03-11 12:55:12 +09001/*
Nobuhiro Iwamatsud76619d2008-03-12 18:02:57 +09002 * Copyright (C) 2007,2008 Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Yusuke Godacf236022008-03-11 12:55:12 +09003 * Copyright (C) 2008 Yusuke Goda <goda.yusuke@renesas.com>
4 *
Wolfgang Denkd79de1d2013-07-08 09:37:19 +02005 * SPDX-License-Identifier: GPL-2.0+
Yusuke Godacf236022008-03-11 12:55:12 +09006 */
7
8#include <common.h>
9#include <ide.h>
10#include <asm/processor.h>
11#include <asm/io.h>
12#include <asm/pci.h>
Ben Warren26425a62008-08-31 09:49:42 -070013#include <netdev.h>
Yusuke Godacf236022008-03-11 12:55:12 +090014#include "r7780mp.h"
15
John Rigby0d21ed02010-12-20 18:27:51 -070016DECLARE_GLOBAL_DATA_PTR;
17
Yusuke Godacf236022008-03-11 12:55:12 +090018int checkboard(void)
19{
20#if defined(CONFIG_R7780MP)
21 puts("BOARD: Renesas Solutions R7780MP\n");
22#else
23 puts("BOARD: Renesas Solutions R7780RP\n");
24#endif
25 return 0;
26}
27
28int board_init(void)
29{
30 /* SCIF Enable */
Nobuhiro Iwamatsu9aa0bd72008-06-17 16:27:41 +090031 writew(0x0, PHCR);
Yusuke Godacf236022008-03-11 12:55:12 +090032
Yusuke Godacf236022008-03-11 12:55:12 +090033 return 0;
34}
35
Nobuhiro Iwamatsu9aa0bd72008-06-17 16:27:41 +090036int dram_init(void)
Yusuke Godacf236022008-03-11 12:55:12 +090037{
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020038 gd->bd->bi_memstart = CONFIG_SYS_SDRAM_BASE;
39 gd->bd->bi_memsize = CONFIG_SYS_SDRAM_SIZE;
40 printf("DRAM: %dMB\n", CONFIG_SYS_SDRAM_SIZE / (1024 * 1024));
Yusuke Godacf236022008-03-11 12:55:12 +090041 return 0;
42}
43
Nobuhiro Iwamatsu9aa0bd72008-06-17 16:27:41 +090044void led_set_state(unsigned short value)
Yusuke Godacf236022008-03-11 12:55:12 +090045{
46
47}
48
Nobuhiro Iwamatsu9aa0bd72008-06-17 16:27:41 +090049void ide_set_reset(int idereset)
Yusuke Godacf236022008-03-11 12:55:12 +090050{
51 /* if reset = 1 IDE reset will be asserted */
Nobuhiro Iwamatsu9aa0bd72008-06-17 16:27:41 +090052 if (idereset) {
53 writew(0x432, FPGA_CFCTL);
Yusuke Godacf236022008-03-11 12:55:12 +090054#if defined(CONFIG_R7780MP)
Nobuhiro Iwamatsu9aa0bd72008-06-17 16:27:41 +090055 writew(inw(FPGA_CFPOW)|0x01, FPGA_CFPOW);
Yusuke Godacf236022008-03-11 12:55:12 +090056#else
Nobuhiro Iwamatsu9aa0bd72008-06-17 16:27:41 +090057 writew(inw(FPGA_CFPOW)|0x02, FPGA_CFPOW);
Yusuke Godacf236022008-03-11 12:55:12 +090058#endif
Nobuhiro Iwamatsu9aa0bd72008-06-17 16:27:41 +090059 writew(0x01, FPGA_CFCDINTCLR);
Yusuke Godacf236022008-03-11 12:55:12 +090060 }
61}
62
Yusuke Godacf236022008-03-11 12:55:12 +090063static struct pci_controller hose;
64void pci_init_board(void)
65{
Nobuhiro Iwamatsu9aa0bd72008-06-17 16:27:41 +090066 pci_sh7780_init(&hose);
Yusuke Godacf236022008-03-11 12:55:12 +090067}
Ben Warren26425a62008-08-31 09:49:42 -070068
69int board_eth_init(bd_t *bis)
70{
Bernhard Kaindladb18ea2011-10-20 10:56:59 +000071 /* return >= 0 if a chip is found, the board's AX88796L is n2k-based */
72 return ne2k_register() + pci_eth_init(bis);
Ben Warren26425a62008-08-31 09:49:42 -070073}