Alex Marginean | 72f3aa5 | 2021-01-27 13:00:00 +0200 | [diff] [blame] | 1 | // SPDX-License-Identifier: GPL-2.0+ OR X11 |
| 2 | /* |
| 3 | * NXP LS1028A-QDS device tree fragment for RCW x3xx |
| 4 | * |
Vladimir Oltean | 5041e42 | 2021-09-17 14:27:13 +0300 | [diff] [blame] | 5 | * Copyright 2019-2021 NXP |
Alex Marginean | 72f3aa5 | 2021-01-27 13:00:00 +0200 | [diff] [blame] | 6 | */ |
| 7 | |
| 8 | /* |
| 9 | * This setup is using a SCH-30841-R card with AQR412 quad PHY in slot 2. This |
| 10 | * is used for the 4 integrated ethernet switch in a multiplexes USXGMII set-up. |
| 11 | * |
| 12 | * We're including the normal .dsti file, not the reworked card .dtsi |
| 13 | * intentionally. We are using multiplexing of the 4 interfaces on a single |
| 14 | * lane and the rework doesn't actually disable any port. The rework is in fact |
| 15 | * needed, otherwise the PHY won't work with the default wiring on the QDS/PHY |
| 16 | * card. |
| 17 | */ |
| 18 | &slot2 { |
| 19 | #include "fsl-sch-30841.dtsi" |
| 20 | }; |
| 21 | |
Michael Walle | 2a20ed1 | 2021-10-13 18:14:15 +0200 | [diff] [blame] | 22 | &enetc_port2 { |
Vladimir Oltean | c32039a | 2021-06-29 20:53:11 +0300 | [diff] [blame] | 23 | status = "okay"; |
| 24 | }; |
| 25 | |
Alex Marginean | 72f3aa5 | 2021-01-27 13:00:00 +0200 | [diff] [blame] | 26 | &mscc_felix { |
| 27 | status = "okay"; |
| 28 | }; |
| 29 | |
| 30 | &mscc_felix_port0 { |
| 31 | status = "okay"; |
| 32 | phy-mode = "usxgmii"; |
Michael Walle | 2da16cd | 2021-10-13 18:14:05 +0200 | [diff] [blame] | 33 | phy-handle = <&{/soc/i2c@2000000/fpga@66/mux-mdio@54/mdio@50/phy@00}>; |
Alex Marginean | 72f3aa5 | 2021-01-27 13:00:00 +0200 | [diff] [blame] | 34 | }; |
| 35 | |
| 36 | &mscc_felix_port1 { |
| 37 | status = "okay"; |
| 38 | phy-mode = "usxgmii"; |
Michael Walle | 2da16cd | 2021-10-13 18:14:05 +0200 | [diff] [blame] | 39 | phy-handle = <&{/soc/i2c@2000000/fpga@66/mux-mdio@54/mdio@50/phy@01}>; |
Alex Marginean | 72f3aa5 | 2021-01-27 13:00:00 +0200 | [diff] [blame] | 40 | }; |
| 41 | |
| 42 | &mscc_felix_port2 { |
| 43 | status = "okay"; |
| 44 | phy-mode = "usxgmii"; |
Michael Walle | 2da16cd | 2021-10-13 18:14:05 +0200 | [diff] [blame] | 45 | phy-handle = <&{/soc/i2c@2000000/fpga@66/mux-mdio@54/mdio@50/phy@02}>; |
Alex Marginean | 72f3aa5 | 2021-01-27 13:00:00 +0200 | [diff] [blame] | 46 | }; |
| 47 | |
| 48 | &mscc_felix_port3 { |
| 49 | status = "okay"; |
| 50 | phy-mode = "usxgmii"; |
Michael Walle | 2da16cd | 2021-10-13 18:14:05 +0200 | [diff] [blame] | 51 | phy-handle = <&{/soc/i2c@2000000/fpga@66/mux-mdio@54/mdio@50/phy@03}>; |
Alex Marginean | 72f3aa5 | 2021-01-27 13:00:00 +0200 | [diff] [blame] | 52 | }; |
Vladimir Oltean | c32039a | 2021-06-29 20:53:11 +0300 | [diff] [blame] | 53 | |
| 54 | &mscc_felix_port4 { |
Michael Walle | 2a20ed1 | 2021-10-13 18:14:15 +0200 | [diff] [blame] | 55 | ethernet = <&enetc_port2>; |
Vladimir Oltean | c32039a | 2021-06-29 20:53:11 +0300 | [diff] [blame] | 56 | status = "okay"; |
| 57 | }; |