blob: 62e818f099cab7c90d8095c667bc79da5e9d0baf [file] [log] [blame]
Alex Marginean72f3aa52021-01-27 13:00:00 +02001// SPDX-License-Identifier: GPL-2.0+ OR X11
2/*
3 * NXP LS1028A-QDS device tree fragment for RCW x3xx
4 *
Vladimir Oltean5041e422021-09-17 14:27:13 +03005 * Copyright 2019-2021 NXP
Alex Marginean72f3aa52021-01-27 13:00:00 +02006 */
7
8/*
9 * This setup is using a SCH-30841-R card with AQR412 quad PHY in slot 2. This
10 * is used for the 4 integrated ethernet switch in a multiplexes USXGMII set-up.
11 *
12 * We're including the normal .dsti file, not the reworked card .dtsi
13 * intentionally. We are using multiplexing of the 4 interfaces on a single
14 * lane and the rework doesn't actually disable any port. The rework is in fact
15 * needed, otherwise the PHY won't work with the default wiring on the QDS/PHY
16 * card.
17 */
18&slot2 {
19#include "fsl-sch-30841.dtsi"
20};
21
Michael Walle2a20ed12021-10-13 18:14:15 +020022&enetc_port2 {
Vladimir Olteanc32039a2021-06-29 20:53:11 +030023 status = "okay";
24};
25
Alex Marginean72f3aa52021-01-27 13:00:00 +020026&mscc_felix {
27 status = "okay";
28};
29
30&mscc_felix_port0 {
31 status = "okay";
32 phy-mode = "usxgmii";
Michael Walle2da16cd2021-10-13 18:14:05 +020033 phy-handle = <&{/soc/i2c@2000000/fpga@66/mux-mdio@54/mdio@50/phy@00}>;
Alex Marginean72f3aa52021-01-27 13:00:00 +020034};
35
36&mscc_felix_port1 {
37 status = "okay";
38 phy-mode = "usxgmii";
Michael Walle2da16cd2021-10-13 18:14:05 +020039 phy-handle = <&{/soc/i2c@2000000/fpga@66/mux-mdio@54/mdio@50/phy@01}>;
Alex Marginean72f3aa52021-01-27 13:00:00 +020040};
41
42&mscc_felix_port2 {
43 status = "okay";
44 phy-mode = "usxgmii";
Michael Walle2da16cd2021-10-13 18:14:05 +020045 phy-handle = <&{/soc/i2c@2000000/fpga@66/mux-mdio@54/mdio@50/phy@02}>;
Alex Marginean72f3aa52021-01-27 13:00:00 +020046};
47
48&mscc_felix_port3 {
49 status = "okay";
50 phy-mode = "usxgmii";
Michael Walle2da16cd2021-10-13 18:14:05 +020051 phy-handle = <&{/soc/i2c@2000000/fpga@66/mux-mdio@54/mdio@50/phy@03}>;
Alex Marginean72f3aa52021-01-27 13:00:00 +020052};
Vladimir Olteanc32039a2021-06-29 20:53:11 +030053
54&mscc_felix_port4 {
Michael Walle2a20ed12021-10-13 18:14:15 +020055 ethernet = <&enetc_port2>;
Vladimir Olteanc32039a2021-06-29 20:53:11 +030056 status = "okay";
57};