| Troy Kisky | 2f95ec9 | 2019-07-29 12:15:54 -0700 | [diff] [blame] | 1 | // SPDX-License-Identifier: GPL-2.0+ |
| 2 | // |
| 3 | // Copyright 2013-2019 Boundary Devices, Inc. |
| 4 | // Copyright 2012 Freescale Semiconductor, Inc. |
| 5 | // Copyright 2011 Linaro Ltd. |
| 6 | |
| 7 | #include "imx6qdl-sabrelite.dtsi" |
| 8 | |
| 9 | &iomuxc { |
| 10 | pinctrl_enet: enetgrp { |
| 11 | fsl,pins = < |
| 12 | MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 |
| 13 | MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 |
| 14 | MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x100b0 |
| 15 | MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x100b0 |
| 16 | MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x100b0 |
| 17 | MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x100b0 |
| 18 | MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x100b0 |
| 19 | MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x100b0 |
| 20 | MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x100b0 |
| 21 | MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0 |
| 22 | MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0 |
| 23 | MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0 |
| 24 | MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0 |
| 25 | MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0 |
| 26 | MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0 |
| 27 | #undef GP_ENET_PHY_RESET |
| 28 | #define GP_ENET_PHY_RESET <&gpio1 27 GPIO_ACTIVE_LOW> |
| 29 | MX6QDL_PAD_ENET_RXD0__GPIO1_IO27 0x030b0 |
| 30 | #define GPIRQ_ENET_PHY <&gpio1 28 IRQ_TYPE_LEVEL_LOW> |
| 31 | MX6QDL_PAD_ENET_TX_EN__GPIO1_IO28 0x1b0b0 |
| 32 | >; |
| 33 | }; |
| 34 | |
| 35 | pinctrl_hog: hoggrp { |
| 36 | fsl,pins = < |
| 37 | /* Spare */ |
| 38 | MX6QDL_PAD_SD3_DAT4__GPIO7_IO01 0x1b0b0 |
| 39 | MX6QDL_PAD_NANDF_D7__GPIO2_IO07 0x1b0b0 |
| 40 | MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x1b0b0 |
| 41 | >; |
| 42 | }; |
| 43 | |
| 44 | pinctrl_uart3: uart3grp { |
| 45 | fsl,pins = < |
| 46 | MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b1 |
| 47 | MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b1 |
| 48 | MX6QDL_PAD_EIM_D23__UART3_CTS_B 0x1b0b1 |
| 49 | MX6QDL_PAD_EIM_D31__UART3_RTS_B 0x1b0b1 |
| 50 | >; |
| 51 | }; |
| 52 | }; |
| 53 | |
| 54 | &fec { |
| 55 | #if 0 |
| 56 | phy-reset-gpios = GP_ENET_PHY_RESET; |
| 57 | #endif |
| 58 | }; |
| 59 | |
| 60 | &uart3 { |
| 61 | pinctrl-names = "default"; |
| 62 | pinctrl-0 = <&pinctrl_uart3>; |
| 63 | uart-has-rtscts; |
| 64 | status = "okay"; |
| 65 | }; |
| 66 | |
| 67 | &usdhc3 { |
| 68 | /delete-property/ wp-gpios; |
| 69 | }; |