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git01.mediatek.com / filogic / uboot / f248ebc95c44705fc9c4066de8861f5e3cb6d356 / . / drivers / bcm570x_lm.h
blob: 607f3fd067caa1775a16ad87673f379b2bc5ebac [file] [log] [blame]
wdenkc6097192002-11-03 00:24:07 +0000[diff] [blame]1
2/******************************************************************************/
3/* */
4/* Broadcom BCM5700 Linux Network Driver, Copyright (c) 2000 Broadcom */
5/* Corporation. */
6/* All rights reserved. */
7/* */
8/* This program is free software; you can redistribute it and/or modify */
9/* it under the terms of the GNU General Public License as published by */
10/* the Free Software Foundation, located in the file LICENSE. */
11/* */
12/* History: */
13/* 02/25/00 Hav Khauv Initial version. */
14/******************************************************************************/
15
16#ifndef LM_H
17#define LM_H
18
19#include "bcm570x_queue.h"
20#include "bcm570x_bits.h"
21
22
wdenkc6097192002-11-03 00:24:07 +0000[diff] [blame]23/******************************************************************************/
24/* Basic types. */
25/******************************************************************************/
26
27typedef char LM_CHAR, *PLM_CHAR;
28typedef unsigned int LM_UINT, *PLM_UINT;
29typedef unsigned char LM_UINT8, *PLM_UINT8;
30typedef unsigned short LM_UINT16, *PLM_UINT16;
31typedef unsigned int LM_UINT32, *PLM_UINT32;
32typedef unsigned int LM_COUNTER, *PLM_COUNTER;
33typedef void LM_VOID, *PLM_VOID;
34typedef char LM_BOOL, *PLM_BOOL;
35
36/* 64bit value. */
37typedef struct {
38#ifdef BIG_ENDIAN_HOST
39 LM_UINT32 High;
40 LM_UINT32 Low;
41#else /* BIG_ENDIAN_HOST */
42 LM_UINT32 Low;
43 LM_UINT32 High;
44#endif /* !BIG_ENDIAN_HOST */
45} LM_UINT64, *PLM_UINT64;
46
47typedef LM_UINT64 LM_PHYSICAL_ADDRESS, *PLM_PHYSICAL_ADDRESS;
48
49/* void LM_INC_PHYSICAL_ADDRESS(PLM_PHYSICAL_ADDRESS pAddr,LM_UINT32 IncSize) */
50#define LM_INC_PHYSICAL_ADDRESS(pAddr, IncSize) \
51 { \
wdenk57b2d802003-06-27 21:31:46 +0000[diff] [blame]52 LM_UINT32 OrgLow; \
53 \
54 OrgLow = (pAddr)->Low; \
55 (pAddr)->Low += IncSize; \
56 if((pAddr)->Low < OrgLow) { \
57 (pAddr)->High++; /* Wrap around. */ \
58 } \
wdenkc6097192002-11-03 00:24:07 +0000[diff] [blame]59 }
60
61
62#ifndef NULL
63#define NULL ((void *) 0)
64#endif /* NULL */
65
66#ifndef OFFSETOF
67#define OFFSETOF(_s, _m) (MM_UINT_PTR(&(((_s *) 0)->_m)))
68#endif /* OFFSETOF */
69
70
wdenkc6097192002-11-03 00:24:07 +0000[diff] [blame]71/******************************************************************************/
72/* Simple macros. */
73/******************************************************************************/
74
75#define IS_ETH_BROADCAST(_pEthAddr) \
76 (((unsigned char *) (_pEthAddr))[0] == ((unsigned char) 0xff))
77
78#define IS_ETH_MULTICAST(_pEthAddr) \
79 (((unsigned char *) (_pEthAddr))[0] & ((unsigned char) 0x01))
80
81#define IS_ETH_ADDRESS_EQUAL(_pEtherAddr1, _pEtherAddr2) \
82 ((((unsigned char *) (_pEtherAddr1))[0] == \
83 ((unsigned char *) (_pEtherAddr2))[0]) && \
84 (((unsigned char *) (_pEtherAddr1))[1] == \
85 ((unsigned char *) (_pEtherAddr2))[1]) && \
86 (((unsigned char *) (_pEtherAddr1))[2] == \
87 ((unsigned char *) (_pEtherAddr2))[2]) && \
88 (((unsigned char *) (_pEtherAddr1))[3] == \
89 ((unsigned char *) (_pEtherAddr2))[3]) && \
90 (((unsigned char *) (_pEtherAddr1))[4] == \
91 ((unsigned char *) (_pEtherAddr2))[4]) && \
92 (((unsigned char *) (_pEtherAddr1))[5] == \
93 ((unsigned char *) (_pEtherAddr2))[5]))
94
95#define COPY_ETH_ADDRESS(_Src, _Dst) \
96 ((unsigned char *) (_Dst))[0] = ((unsigned char *) (_Src))[0]; \
97 ((unsigned char *) (_Dst))[1] = ((unsigned char *) (_Src))[1]; \
98 ((unsigned char *) (_Dst))[2] = ((unsigned char *) (_Src))[2]; \
99 ((unsigned char *) (_Dst))[3] = ((unsigned char *) (_Src))[3]; \
100 ((unsigned char *) (_Dst))[4] = ((unsigned char *) (_Src))[4]; \
101 ((unsigned char *) (_Dst))[5] = ((unsigned char *) (_Src))[5];
102
103
wdenkc6097192002-11-03 00:24:07 +0000[diff] [blame]104/******************************************************************************/
105/* Constants. */
106/******************************************************************************/
107
108#define ETHERNET_ADDRESS_SIZE 6
109#define ETHERNET_PACKET_HEADER_SIZE 14
110#define MIN_ETHERNET_PACKET_SIZE 64 /* with 4 byte crc. */
111#define MAX_ETHERNET_PACKET_SIZE 1518 /* with 4 byte crc. */
112#define MIN_ETHERNET_PACKET_SIZE_NO_CRC 60
113#define MAX_ETHERNET_PACKET_SIZE_NO_CRC 1514
114#define MAX_ETHERNET_PACKET_BUFFER_SIZE 1536 /* A nice even number. */
115
116#ifndef LM_MAX_MC_TABLE_SIZE
117#define LM_MAX_MC_TABLE_SIZE 32
118#endif /* LM_MAX_MC_TABLE_SIZE */
119#define LM_MC_ENTRY_SIZE (ETHERNET_ADDRESS_SIZE+1)
120#define LM_MC_INSTANCE_COUNT_INDEX (LM_MC_ENTRY_SIZE-1)
121
122
123/* Receive filter masks. */
124#define LM_ACCEPT_UNICAST 0x0001
125#define LM_ACCEPT_MULTICAST 0x0002
126#define LM_ACCEPT_ALL_MULTICAST 0x0004
127#define LM_ACCEPT_BROADCAST 0x0008
128#define LM_ACCEPT_ERROR_PACKET 0x0010
129
130#define LM_PROMISCUOUS_MODE 0x10000
131
132
wdenkc6097192002-11-03 00:24:07 +0000[diff] [blame]133/******************************************************************************/
134/* PCI registers. */
135/******************************************************************************/
136
137#define PCI_VENDOR_ID_REG 0x00
138#define PCI_DEVICE_ID_REG 0x02
139
140#define PCI_COMMAND_REG 0x04
141#define PCI_IO_SPACE_ENABLE 0x0001
142#define PCI_MEM_SPACE_ENABLE 0x0002
143#define PCI_BUSMASTER_ENABLE 0x0004
144#define PCI_MEMORY_WRITE_INVALIDATE 0x0010
145#define PCI_PARITY_ERROR_ENABLE 0x0040
146#define PCI_SYSTEM_ERROR_ENABLE 0x0100
147#define PCI_FAST_BACK_TO_BACK_ENABLE 0x0200
148
149#define PCI_STATUS_REG 0x06
150#define PCI_REV_ID_REG 0x08
151
152#define PCI_CACHE_LINE_SIZE_REG 0x0c
153
154#define PCI_IO_BASE_ADDR_REG 0x10
155#define PCI_IO_BASE_ADDR_MASK 0xfffffff0
156
157#define PCI_MEM_BASE_ADDR_LOW 0x10
158#define PCI_MEM_BASE_ADDR_HIGH 0x14
159
160#define PCI_SUBSYSTEM_VENDOR_ID_REG 0x2c
161#define PCI_SUBSYSTEM_ID_REG 0x2e
162#define PCI_INT_LINE_REG 0x3c
163
164#define PCIX_CAP_REG 0x40
165#define PCIX_ENABLE_RELAXED_ORDERING BIT_17
166
167/******************************************************************************/
168/* Fragment structure. */
169/******************************************************************************/
170
171typedef struct {
172 LM_UINT32 FragSize;
173 LM_PHYSICAL_ADDRESS FragBuf;
174} LM_FRAG, *PLM_FRAG;
175
176typedef struct {
177 /* FragCount is initialized for the caller to the maximum array size, on */
178 /* return FragCount is the number of the actual fragments in the array. */
179 LM_UINT32 FragCount;
180
181 /* Total buffer size. */
182 LM_UINT32 TotalSize;
183
184 /* Fragment array buffer. */
185 LM_FRAG Fragments[1];
186} LM_FRAG_LIST, *PLM_FRAG_LIST;
187
188#define DECLARE_FRAG_LIST_BUFFER_TYPE(_FRAG_LIST_TYPE_NAME, _MAX_FRAG_COUNT) \
189 typedef struct { \
wdenk57b2d802003-06-27 21:31:46 +0000[diff] [blame]190 LM_FRAG_LIST FragList; \
191 LM_FRAG FragListBuffer[_MAX_FRAG_COUNT-1]; \
wdenkc6097192002-11-03 00:24:07 +0000[diff] [blame]192 } _FRAG_LIST_TYPE_NAME, *P##_FRAG_LIST_TYPE_NAME
193
194
wdenkc6097192002-11-03 00:24:07 +0000[diff] [blame]195/******************************************************************************/
196/* Status codes. */
197/******************************************************************************/
198
199#define LM_STATUS_SUCCESS 0
200#define LM_STATUS_FAILURE 1
201
202#define LM_STATUS_INTERRUPT_ACTIVE 2
203#define LM_STATUS_INTERRUPT_NOT_ACTIVE 3
204
205#define LM_STATUS_LINK_ACTIVE 4
206#define LM_STATUS_LINK_DOWN 5
207#define LM_STATUS_LINK_SETTING_MISMATCH 6
208
209#define LM_STATUS_TOO_MANY_FRAGMENTS 7
210#define LM_STATUS_TRANSMIT_ABORTED 8
211#define LM_STATUS_TRANSMIT_ERROR 9
212#define LM_STATUS_RECEIVE_ABORTED 10
213#define LM_STATUS_RECEIVE_ERROR 11
214#define LM_STATUS_INVALID_PACKET_SIZE 12
215#define LM_STATUS_OUT_OF_MAP_REGISTERS 13
216#define LM_STATUS_UNKNOWN_ADAPTER 14
217
218typedef LM_UINT LM_STATUS, *PLM_STATUS;
219
220
wdenkc6097192002-11-03 00:24:07 +0000[diff] [blame]221/******************************************************************************/
222/* Requested media type. */
223/******************************************************************************/
224
225#define LM_REQUESTED_MEDIA_TYPE_AUTO 0
226#define LM_REQUESTED_MEDIA_TYPE_BNC 1
227#define LM_REQUESTED_MEDIA_TYPE_UTP_AUTO 2
228#define LM_REQUESTED_MEDIA_TYPE_UTP_10MBPS 3
229#define LM_REQUESTED_MEDIA_TYPE_UTP_10MBPS_FULL_DUPLEX 4
230#define LM_REQUESTED_MEDIA_TYPE_UTP_100MBPS 5
231#define LM_REQUESTED_MEDIA_TYPE_UTP_100MBPS_FULL_DUPLEX 6
232#define LM_REQUESTED_MEDIA_TYPE_UTP_1000MBPS 7
233#define LM_REQUESTED_MEDIA_TYPE_UTP_1000MBPS_FULL_DUPLEX 8
234#define LM_REQUESTED_MEDIA_TYPE_FIBER_100MBPS 9
235#define LM_REQUESTED_MEDIA_TYPE_FIBER_100MBPS_FULL_DUPLEX 10
236#define LM_REQUESTED_MEDIA_TYPE_FIBER_1000MBPS 11
237#define LM_REQUESTED_MEDIA_TYPE_FIBER_1000MBPS_FULL_DUPLEX 12
238#define LM_REQUESTED_MEDIA_TYPE_MAC_LOOPBACK 0xfffe
239#define LM_REQUESTED_MEDIA_TYPE_PHY_LOOPBACK 0xffff
240
241typedef LM_UINT32 LM_REQUESTED_MEDIA_TYPE, *PLM_REQUESTED_MEDIA_TYPE;
242
243
wdenkc6097192002-11-03 00:24:07 +0000[diff] [blame]244/******************************************************************************/
245/* Media type. */
246/******************************************************************************/
247
248#define LM_MEDIA_TYPE_UNKNOWN -1
249#define LM_MEDIA_TYPE_AUTO 0
250#define LM_MEDIA_TYPE_UTP 1
251#define LM_MEDIA_TYPE_BNC 2
252#define LM_MEDIA_TYPE_AUI 3
253#define LM_MEDIA_TYPE_FIBER 4
254
255typedef LM_UINT32 LM_MEDIA_TYPE, *PLM_MEDIA_TYPE;
256
257
wdenkc6097192002-11-03 00:24:07 +0000[diff] [blame]258/******************************************************************************/
259/* Line speed. */
260/******************************************************************************/
261
262#define LM_LINE_SPEED_UNKNOWN 0
263#define LM_LINE_SPEED_10MBPS 1
264#define LM_LINE_SPEED_100MBPS 2
265#define LM_LINE_SPEED_1000MBPS 3
266
267typedef LM_UINT32 LM_LINE_SPEED, *PLM_LINE_SPEED;
268
269
wdenkc6097192002-11-03 00:24:07 +0000[diff] [blame]270/******************************************************************************/
271/* Duplex mode. */
272/******************************************************************************/
273
274#define LM_DUPLEX_MODE_UNKNOWN 0
275#define LM_DUPLEX_MODE_HALF 1
276#define LM_DUPLEX_MODE_FULL 2
277
278typedef LM_UINT32 LM_DUPLEX_MODE, *PLM_DUPLEX_MODE;
279
280
wdenkc6097192002-11-03 00:24:07 +0000[diff] [blame]281/******************************************************************************/
282/* Power state. */
283/******************************************************************************/
284
285#define LM_POWER_STATE_D0 0
286#define LM_POWER_STATE_D1 1
287#define LM_POWER_STATE_D2 2
288#define LM_POWER_STATE_D3 3
289
290typedef LM_UINT32 LM_POWER_STATE, *PLM_POWER_STATE;
291
292
wdenkc6097192002-11-03 00:24:07 +0000[diff] [blame]293/******************************************************************************/
294/* Task offloading. */
295/******************************************************************************/
296
297#define LM_TASK_OFFLOAD_NONE 0x0000
298#define LM_TASK_OFFLOAD_TX_IP_CHECKSUM 0x0001
299#define LM_TASK_OFFLOAD_RX_IP_CHECKSUM 0x0002
300#define LM_TASK_OFFLOAD_TX_TCP_CHECKSUM 0x0004
301#define LM_TASK_OFFLOAD_RX_TCP_CHECKSUM 0x0008
302#define LM_TASK_OFFLOAD_TX_UDP_CHECKSUM 0x0010
303#define LM_TASK_OFFLOAD_RX_UDP_CHECKSUM 0x0020
304#define LM_TASK_OFFLOAD_TCP_SEGMENTATION 0x0040
305
306typedef LM_UINT32 LM_TASK_OFFLOAD, *PLM_TASK_OFFLOAD;
307
308
wdenkc6097192002-11-03 00:24:07 +0000[diff] [blame]309/******************************************************************************/
310/* Flow control. */
311/******************************************************************************/
312
313#define LM_FLOW_CONTROL_NONE 0x00
314#define LM_FLOW_CONTROL_RECEIVE_PAUSE 0x01
315#define LM_FLOW_CONTROL_TRANSMIT_PAUSE 0x02
316#define LM_FLOW_CONTROL_RX_TX_PAUSE (LM_FLOW_CONTROL_RECEIVE_PAUSE | \
317 LM_FLOW_CONTROL_TRANSMIT_PAUSE)
318
319/* This value can be or-ed with RECEIVE_PAUSE and TRANSMIT_PAUSE. If the */
320/* auto-negotiation is disabled and the RECEIVE_PAUSE and TRANSMIT_PAUSE */
321/* bits are set, then flow control is enabled regardless of link partner's */
322/* flow control capability. */
323#define LM_FLOW_CONTROL_AUTO_PAUSE 0x80000000
324
325typedef LM_UINT32 LM_FLOW_CONTROL, *PLM_FLOW_CONTROL;
326
327
wdenkc6097192002-11-03 00:24:07 +0000[diff] [blame]328/******************************************************************************/
329/* Wake up mode. */
330/******************************************************************************/
331
332#define LM_WAKE_UP_MODE_NONE 0
333#define LM_WAKE_UP_MODE_MAGIC_PACKET 1
334#define LM_WAKE_UP_MODE_NWUF 2
335#define LM_WAKE_UP_MODE_LINK_CHANGE 4
336
337typedef LM_UINT32 LM_WAKE_UP_MODE, *PLM_WAKE_UP_MODE;
338
339
wdenkc6097192002-11-03 00:24:07 +0000[diff] [blame]340/******************************************************************************/
341/* Counters. */
342/******************************************************************************/
343
344#define LM_COUNTER_FRAMES_XMITTED_OK 0
345#define LM_COUNTER_FRAMES_RECEIVED_OK 1
346#define LM_COUNTER_ERRORED_TRANSMIT_COUNT 2
347#define LM_COUNTER_ERRORED_RECEIVE_COUNT 3
348#define LM_COUNTER_RCV_CRC_ERROR 4
349#define LM_COUNTER_ALIGNMENT_ERROR 5
350#define LM_COUNTER_SINGLE_COLLISION_FRAMES 6
351#define LM_COUNTER_MULTIPLE_COLLISION_FRAMES 7
352#define LM_COUNTER_FRAMES_DEFERRED 8
353#define LM_COUNTER_MAX_COLLISIONS 9
354#define LM_COUNTER_RCV_OVERRUN 10
355#define LM_COUNTER_XMIT_UNDERRUN 11
356#define LM_COUNTER_UNICAST_FRAMES_XMIT 12
357#define LM_COUNTER_MULTICAST_FRAMES_XMIT 13
358#define LM_COUNTER_BROADCAST_FRAMES_XMIT 14
359#define LM_COUNTER_UNICAST_FRAMES_RCV 15
360#define LM_COUNTER_MULTICAST_FRAMES_RCV 16
361#define LM_COUNTER_BROADCAST_FRAMES_RCV 17
362
363typedef LM_UINT32 LM_COUNTER_TYPE, *PLM_COUNTER_TYPE;
364
365
wdenkc6097192002-11-03 00:24:07 +0000[diff] [blame]366/******************************************************************************/
367/* Forward definition. */
368/******************************************************************************/
369
370typedef struct _LM_DEVICE_BLOCK *PLM_DEVICE_BLOCK;
371typedef struct _LM_PACKET *PLM_PACKET;
372
373
wdenkc6097192002-11-03 00:24:07 +0000[diff] [blame]374/******************************************************************************/
375/* Function prototypes. */
376/******************************************************************************/
377
378LM_STATUS LM_GetAdapterInfo(PLM_DEVICE_BLOCK pDevice);
379LM_STATUS LM_InitializeAdapter(PLM_DEVICE_BLOCK pDevice);
380LM_STATUS LM_ResetAdapter(PLM_DEVICE_BLOCK pDevice);
381LM_STATUS LM_DisableInterrupt(PLM_DEVICE_BLOCK pDevice);
382LM_STATUS LM_EnableInterrupt(PLM_DEVICE_BLOCK pDevice);
383LM_STATUS LM_SendPacket(PLM_DEVICE_BLOCK pDevice, PLM_PACKET pPacket);
384LM_STATUS LM_ServiceInterrupts(PLM_DEVICE_BLOCK pDevice);
385LM_STATUS LM_QueueRxPackets(PLM_DEVICE_BLOCK pDevice);
386LM_STATUS LM_SetReceiveMask(PLM_DEVICE_BLOCK pDevice, LM_UINT32 Mask);
387LM_STATUS LM_Halt(PLM_DEVICE_BLOCK pDevice);
388LM_STATUS LM_Abort(PLM_DEVICE_BLOCK pDevice);
389LM_STATUS LM_MulticastAdd(PLM_DEVICE_BLOCK pDevice, PLM_UINT8 pMcAddress);
390LM_STATUS LM_MulticastDel(PLM_DEVICE_BLOCK pDevice, PLM_UINT8 pMcAddress);
391LM_STATUS LM_MulticastClear(PLM_DEVICE_BLOCK pDevice);
392LM_STATUS LM_SetMacAddress(PLM_DEVICE_BLOCK pDevice, PLM_UINT8 pMacAddress);
393LM_STATUS LM_LoopbackAddress(PLM_DEVICE_BLOCK pDevice, PLM_UINT8 pAddress);
394
395LM_UINT32 LM_GetCrcCounter(PLM_DEVICE_BLOCK pDevice);
396
397LM_WAKE_UP_MODE LM_PMCapabilities(PLM_DEVICE_BLOCK pDevice);
398LM_STATUS LM_NwufAdd(PLM_DEVICE_BLOCK pDevice, LM_UINT32 ByteMaskSize,
399 LM_UINT8 *pByteMask, LM_UINT8 *pPattern);
400LM_STATUS LM_NwufRemove(PLM_DEVICE_BLOCK pDevice, LM_UINT32 ByteMaskSize,
401 LM_UINT8 *pByteMask, LM_UINT8 *pPattern);
402LM_STATUS LM_SetPowerState(PLM_DEVICE_BLOCK pDevice, LM_POWER_STATE PowerLevel);
403
404LM_VOID LM_ReadPhy(PLM_DEVICE_BLOCK pDevice, LM_UINT32 PhyReg,
405 PLM_UINT32 pData32);
406LM_VOID LM_WritePhy(PLM_DEVICE_BLOCK pDevice, LM_UINT32 PhyReg,
407 LM_UINT32 Data32);
408
409LM_STATUS LM_ControlLoopBack(PLM_DEVICE_BLOCK pDevice, LM_UINT32 Control);
410LM_STATUS LM_SetupPhy(PLM_DEVICE_BLOCK pDevice);
411int LM_BlinkLED(PLM_DEVICE_BLOCK pDevice, LM_UINT32 BlinkDuration);
412
413
wdenkc6097192002-11-03 00:24:07 +0000[diff] [blame]414/******************************************************************************/
415/* These are the OS specific functions called by LMAC. */
416/******************************************************************************/
417
418LM_STATUS MM_ReadConfig16(PLM_DEVICE_BLOCK pDevice, LM_UINT32 Offset,
419 LM_UINT16 *pValue16);
420LM_STATUS MM_WriteConfig16(PLM_DEVICE_BLOCK pDevice, LM_UINT32 Offset,
421 LM_UINT16 Value16);
422LM_STATUS MM_ReadConfig32(PLM_DEVICE_BLOCK pDevice, LM_UINT32 Offset,
423 LM_UINT32 *pValue32);
424LM_STATUS MM_WriteConfig32(PLM_DEVICE_BLOCK pDevice, LM_UINT32 Offset,
425 LM_UINT32 Value32);
426LM_STATUS MM_MapMemBase(PLM_DEVICE_BLOCK pDevice);
427LM_STATUS MM_MapIoBase(PLM_DEVICE_BLOCK pDevice);
428LM_STATUS MM_IndicateRxPackets(PLM_DEVICE_BLOCK pDevice);
429LM_STATUS MM_IndicateTxPackets(PLM_DEVICE_BLOCK pDevice);
430LM_STATUS MM_StartTxDma(PLM_DEVICE_BLOCK pDevice, PLM_PACKET pPacket);
431LM_STATUS MM_CompleteTxDma(PLM_DEVICE_BLOCK pDevice, PLM_PACKET pPacket);
432LM_STATUS MM_AllocateMemory(PLM_DEVICE_BLOCK pDevice, LM_UINT32 BlockSize,
433 PLM_VOID *pMemoryBlockVirt);
434LM_STATUS MM_AllocateSharedMemory(PLM_DEVICE_BLOCK pDevice, LM_UINT32 BlockSize,
435 PLM_VOID *pMemoryBlockVirt, PLM_PHYSICAL_ADDRESS pMemoryBlockPhy,
436 LM_BOOL Cached);
437LM_STATUS MM_GetConfig(PLM_DEVICE_BLOCK pDevice);
438LM_STATUS MM_IndicateStatus(PLM_DEVICE_BLOCK pDevice, LM_STATUS Status);
439LM_STATUS MM_InitializeUmPackets(PLM_DEVICE_BLOCK pDevice);
440LM_STATUS MM_FreeRxBuffer(PLM_DEVICE_BLOCK pDevice, PLM_PACKET pPacket);
441LM_STATUS MM_CoalesceTxBuffer(PLM_DEVICE_BLOCK pDevice, PLM_PACKET pPacket);
442LM_STATUS LM_MbufWorkAround(PLM_DEVICE_BLOCK pDevice);
443LM_STATUS LM_SetLinkSpeed(PLM_DEVICE_BLOCK pDevice,
444 LM_REQUESTED_MEDIA_TYPE RequestedMediaType);
445
446#if INCLUDE_5703_A0_FIX
447LM_STATUS LM_Load5703DmaWFirmware(PLM_DEVICE_BLOCK pDevice);
448#endif
449
450
451#endif /* LM_H */