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git01.mediatek.com / filogic / uboot / f20b71846fe1b13f411524377e4aa933d8d10c11 / . / arch / arm / dts / socfpga_cyclone5_mcvevk.dts
blob: 65bec1536f59322dea61fad006f5516c5938cb5d [file] [log] [blame]
Tom Rini10e47792018-05-06 17:58:06 -0400[diff] [blame]1// SPDX-License-Identifier: GPL-2.0+
Marek Vasut8e8b62a2015-08-03 01:37:28 +0200[diff] [blame]2/*
3 * Copyright (C) 2015 Marek Vasut <marex@denx.de>
Marek Vasut8e8b62a2015-08-03 01:37:28 +0200[diff] [blame]4 */
5
6#include "socfpga_cyclone5.dtsi"
7
8/ {
Marek Vasut9d6c56b2017-04-05 13:17:03 +0200[diff] [blame]9 model = "Aries MCVEVK";
Marek Vasut8e8b62a2015-08-03 01:37:28 +0200[diff] [blame]10 compatible = "altr,socfpga-cyclone5", "altr,socfpga";
11
12 chosen {
13 bootargs = "console=ttyS0,115200";
14 };
15
16 aliases {
17 ethernet0 = &gmac0;
Marek Vasutbc71b042015-12-05 19:24:22 +0100[diff] [blame]18 udc0 = &usb1;
Marek Vasut8e8b62a2015-08-03 01:37:28 +0200[diff] [blame]19 };
20
21 memory {
22 name = "memory";
23 device_type = "memory";
24 reg = <0x0 0x40000000>; /* 1GB */
25 };
26
27 soc {
28 u-boot,dm-pre-reloc;
29 };
30};
31
32&gmac0 {
33 status = "okay";
34 phy-mode = "rgmii";
35};
36
37&gpio0 {
38 status = "okay";
39};
40
41&gpio1 {
42 status = "okay";
43};
44
45&gpio2 {
46 status = "okay";
47};
48
49&mmc0 {
50 status = "okay";
51 bus-width = <8>;
52 u-boot,dm-pre-reloc;
53};
Marek Vasutbc71b042015-12-05 19:24:22 +0100[diff] [blame]54
55&usb1 {
Marek Vasut4983df62016-12-05 18:17:52 +0100[diff] [blame]56 disable-over-current;
Marek Vasutbc71b042015-12-05 19:24:22 +0100[diff] [blame]57 status = "okay";
58};