Priyanka Jain | c42c989 | 2013-10-18 17:19:23 +0530 | [diff] [blame] | 1 | /* |
| 2 | * Copyright 2013 Freescale Semiconductor, Inc. |
| 3 | * |
| 4 | * See file CREDITS for list of people who contributed to this |
| 5 | * project. |
| 6 | * |
| 7 | * This program is free software; you can redistribute it and/or |
| 8 | * modify it under the terms of the GNU General Public License as |
| 9 | * published by the Free Software Foundation; either version 2 of |
| 10 | * the License, or (at your option) any later version. |
| 11 | * |
| 12 | * This program is distributed in the hope that it will be useful, |
| 13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 15 | * GNU General Public License for more details. |
| 16 | * |
| 17 | * You should have received a copy of the GNU General Public License |
| 18 | * along with this program; if not, write to the Free Software |
| 19 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
| 20 | * MA 02111-1307 USA |
| 21 | */ |
| 22 | |
| 23 | #ifndef __CONFIG_H |
| 24 | #define __CONFIG_H |
| 25 | |
| 26 | /* |
| 27 | * T1042RDB_PI board configuration file |
| 28 | */ |
| 29 | #define CONFIG_T104xRDB |
| 30 | #define CONFIG_T1042RDB_PI |
| 31 | #define CONFIG_PHYS_64BIT |
| 32 | |
| 33 | #ifdef CONFIG_RAMBOOT_PBL |
| 34 | #define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE |
| 35 | #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc |
| 36 | #endif |
| 37 | |
| 38 | /* High Level Configuration Options */ |
| 39 | #define CONFIG_BOOKE |
| 40 | #define CONFIG_E500 /* BOOKE e500 family */ |
| 41 | #define CONFIG_E500MC /* BOOKE e500mc family */ |
| 42 | #define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */ |
| 43 | #define CONFIG_MPC85xx /* MPC85xx/PQ3 platform */ |
| 44 | #define CONFIG_MP /* support multiple processors */ |
| 45 | |
| 46 | #ifndef CONFIG_SYS_TEXT_BASE |
Prabhakar Kushwaha | f203656 | 2014-01-14 11:34:26 +0530 | [diff] [blame^] | 47 | #define CONFIG_SYS_TEXT_BASE 0xeff40000 |
Priyanka Jain | c42c989 | 2013-10-18 17:19:23 +0530 | [diff] [blame] | 48 | #endif |
| 49 | |
| 50 | #ifndef CONFIG_RESET_VECTOR_ADDRESS |
| 51 | #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc |
| 52 | #endif |
| 53 | |
| 54 | #define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */ |
| 55 | #define CONFIG_SYS_NUM_CPC CONFIG_NUM_DDR_CONTROLLERS |
| 56 | #define CONFIG_FSL_IFC /* Enable IFC Support */ |
| 57 | #define CONFIG_PCI /* Enable PCI/PCIE */ |
| 58 | #define CONFIG_PCI_INDIRECT_BRIDGE |
| 59 | #define CONFIG_PCIE1 /* PCIE controler 1 */ |
| 60 | #define CONFIG_PCIE2 /* PCIE controler 2 */ |
| 61 | #define CONFIG_PCIE3 /* PCIE controler 3 */ |
| 62 | #define CONFIG_PCIE4 /* PCIE controler 4 */ |
| 63 | |
| 64 | #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ |
| 65 | #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ |
| 66 | |
| 67 | #define CONFIG_FSL_LAW /* Use common FSL init code */ |
| 68 | |
| 69 | #define CONFIG_ENV_OVERWRITE |
| 70 | |
| 71 | #ifdef CONFIG_SYS_NO_FLASH |
| 72 | #define CONFIG_ENV_IS_NOWHERE |
| 73 | #else |
| 74 | #define CONFIG_FLASH_CFI_DRIVER |
| 75 | #define CONFIG_SYS_FLASH_CFI |
| 76 | #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE |
| 77 | #endif |
| 78 | |
| 79 | #ifndef CONFIG_SYS_NO_FLASH |
| 80 | #if defined(CONFIG_SPIFLASH) |
| 81 | #define CONFIG_SYS_EXTRA_ENV_RELOC |
| 82 | #define CONFIG_ENV_IS_IN_SPI_FLASH |
| 83 | #define CONFIG_ENV_SPI_BUS 0 |
| 84 | #define CONFIG_ENV_SPI_CS 0 |
| 85 | #define CONFIG_ENV_SPI_MAX_HZ 10000000 |
| 86 | #define CONFIG_ENV_SPI_MODE 0 |
| 87 | #define CONFIG_ENV_SIZE 0x2000 /* 8KB */ |
| 88 | #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */ |
| 89 | #define CONFIG_ENV_SECT_SIZE 0x10000 |
| 90 | #elif defined(CONFIG_SDCARD) |
| 91 | #define CONFIG_SYS_EXTRA_ENV_RELOC |
| 92 | #define CONFIG_ENV_IS_IN_MMC |
| 93 | #define CONFIG_SYS_MMC_ENV_DEV 0 |
| 94 | #define CONFIG_ENV_SIZE 0x2000 |
Prabhakar Kushwaha | f203656 | 2014-01-14 11:34:26 +0530 | [diff] [blame^] | 95 | #define CONFIG_ENV_OFFSET (512 * 1658) |
Priyanka Jain | c42c989 | 2013-10-18 17:19:23 +0530 | [diff] [blame] | 96 | #elif defined(CONFIG_NAND) |
| 97 | #define CONFIG_SYS_EXTRA_ENV_RELOC |
| 98 | #define CONFIG_ENV_IS_IN_NAND |
| 99 | #define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE |
Prabhakar Kushwaha | f203656 | 2014-01-14 11:34:26 +0530 | [diff] [blame^] | 100 | #define CONFIG_ENV_OFFSET (3 * CONFIG_SYS_NAND_BLOCK_SIZE) |
Priyanka Jain | c42c989 | 2013-10-18 17:19:23 +0530 | [diff] [blame] | 101 | #else |
| 102 | #define CONFIG_ENV_IS_IN_FLASH |
| 103 | #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) |
| 104 | #define CONFIG_ENV_SIZE 0x2000 |
| 105 | #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ |
| 106 | #endif |
| 107 | #else /* CONFIG_SYS_NO_FLASH */ |
| 108 | #define CONFIG_ENV_SIZE 0x2000 |
| 109 | #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ |
| 110 | #endif |
| 111 | |
| 112 | #define CONFIG_SYS_CLK_FREQ 100000000 |
| 113 | #define CONFIG_DDR_CLK_FREQ 66666666 |
| 114 | |
| 115 | /* |
| 116 | * These can be toggled for performance analysis, otherwise use default. |
| 117 | */ |
| 118 | #define CONFIG_SYS_CACHE_STASHING |
| 119 | #define CONFIG_BACKSIDE_L2_CACHE |
| 120 | #define CONFIG_SYS_INIT_L2CSR0 L2CSR0_L2E |
| 121 | #define CONFIG_BTB /* toggle branch predition */ |
| 122 | #define CONFIG_DDR_ECC |
| 123 | #ifdef CONFIG_DDR_ECC |
| 124 | #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER |
| 125 | #define CONFIG_MEM_INIT_VALUE 0xdeadbeef |
| 126 | #endif |
| 127 | |
| 128 | #define CONFIG_ENABLE_36BIT_PHYS |
| 129 | |
| 130 | #define CONFIG_ADDR_MAP |
| 131 | #define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */ |
| 132 | |
| 133 | #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */ |
| 134 | #define CONFIG_SYS_MEMTEST_END 0x00400000 |
| 135 | #define CONFIG_SYS_ALT_MEMTEST |
| 136 | #define CONFIG_PANIC_HANG /* do not reset board on panic */ |
| 137 | |
| 138 | /* |
| 139 | * Config the L3 Cache as L3 SRAM |
| 140 | */ |
| 141 | #define CONFIG_SYS_INIT_L3_ADDR 0xFFFC0000 |
| 142 | |
| 143 | #define CONFIG_SYS_DCSRBAR 0xf0000000 |
| 144 | #define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull |
| 145 | |
| 146 | /* |
| 147 | * DDR Setup |
| 148 | */ |
| 149 | #define CONFIG_VERY_BIG_RAM |
| 150 | #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 |
| 151 | #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE |
| 152 | |
| 153 | /* CONFIG_NUM_DDR_CONTROLLERS is defined in include/asm/config_mpc85xx.h */ |
| 154 | #define CONFIG_DIMM_SLOTS_PER_CTLR 1 |
| 155 | #define CONFIG_CHIP_SELECTS_PER_CTRL (4 * CONFIG_DIMM_SLOTS_PER_CTLR) |
| 156 | |
| 157 | #define CONFIG_DDR_SPD |
| 158 | #define CONFIG_SYS_DDR_RAW_TIMING |
York Sun | f062659 | 2013-09-30 09:22:09 -0700 | [diff] [blame] | 159 | #define CONFIG_SYS_FSL_DDR3 |
Priyanka Jain | c42c989 | 2013-10-18 17:19:23 +0530 | [diff] [blame] | 160 | |
| 161 | #define CONFIG_SYS_SPD_BUS_NUM 0 |
| 162 | #define SPD_EEPROM_ADDRESS 0x51 |
| 163 | |
| 164 | #define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */ |
| 165 | |
| 166 | /* |
| 167 | * IFC Definitions |
| 168 | */ |
| 169 | #define CONFIG_SYS_FLASH_BASE 0xe8000000 |
| 170 | #define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE) |
| 171 | |
| 172 | #define CONFIG_SYS_NOR_CSPR_EXT (0xf) |
| 173 | #define CONFIG_SYS_NOR_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE) | \ |
| 174 | CSPR_PORT_SIZE_16 | \ |
| 175 | CSPR_MSEL_NOR | \ |
| 176 | CSPR_V) |
| 177 | #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024) |
| 178 | /* NOR Flash Timing Params */ |
| 179 | #define CONFIG_SYS_NOR_CSOR CSOR_NAND_TRHZ_80 |
| 180 | #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \ |
| 181 | FTIM0_NOR_TEADC(0x5) | \ |
| 182 | FTIM0_NOR_TEAHC(0x5)) |
| 183 | #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \ |
| 184 | FTIM1_NOR_TRAD_NOR(0x1A) |\ |
| 185 | FTIM1_NOR_TSEQRAD_NOR(0x13)) |
| 186 | #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \ |
| 187 | FTIM2_NOR_TCH(0x4) | \ |
| 188 | FTIM2_NOR_TWPH(0x0E) | \ |
| 189 | FTIM2_NOR_TWP(0x1c)) |
| 190 | #define CONFIG_SYS_NOR_FTIM3 0x0 |
| 191 | |
| 192 | #define CONFIG_SYS_FLASH_QUIET_TEST |
| 193 | #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ |
| 194 | |
| 195 | #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ |
| 196 | #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ |
| 197 | #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ |
| 198 | #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ |
| 199 | |
| 200 | #define CONFIG_SYS_FLASH_EMPTY_INFO |
| 201 | #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS} |
| 202 | |
| 203 | /* CPLD on IFC */ |
| 204 | #define CONFIG_SYS_CPLD_BASE 0xffdf0000 |
| 205 | #define CONFIG_SYS_CPLD_BASE_PHYS (0xf00000000ull | CONFIG_SYS_CPLD_BASE) |
| 206 | #define CONFIG_SYS_CSPR2 (CSPR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE_PHYS) \ |
| 207 | | CSPR_PORT_SIZE_8 \ |
| 208 | | CSPR_MSEL_GPCM \ |
| 209 | | CSPR_V) |
| 210 | #define CONFIG_SYS_AMASK2 IFC_AMASK(64*1024) |
| 211 | #define CONFIG_SYS_CSOR2 0x0 |
| 212 | /* CPLD Timing parameters for IFC CS2 */ |
| 213 | #define CONFIG_SYS_CS2_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \ |
| 214 | FTIM0_GPCM_TEADC(0x0e) | \ |
| 215 | FTIM0_GPCM_TEAHC(0x0e)) |
| 216 | #define CONFIG_SYS_CS2_FTIM1 (FTIM1_GPCM_TACO(0x0e) | \ |
| 217 | FTIM1_GPCM_TRAD(0x1f)) |
| 218 | #define CONFIG_SYS_CS2_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \ |
| 219 | FTIM2_GPCM_TCH(0x0) | \ |
| 220 | FTIM2_GPCM_TWP(0x1f)) |
| 221 | #define CONFIG_SYS_CS2_FTIM3 0x0 |
| 222 | |
| 223 | /* NAND Flash on IFC */ |
| 224 | #define CONFIG_NAND_FSL_IFC |
| 225 | #define CONFIG_SYS_NAND_BASE 0xff800000 |
| 226 | #define CONFIG_SYS_NAND_BASE_PHYS (0xf00000000ull | CONFIG_SYS_NAND_BASE) |
| 227 | |
| 228 | #define CONFIG_SYS_NAND_CSPR_EXT (0xf) |
| 229 | #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ |
| 230 | | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \ |
| 231 | | CSPR_MSEL_NAND /* MSEL = NAND */ \ |
| 232 | | CSPR_V) |
| 233 | #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024) |
| 234 | |
| 235 | #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ |
| 236 | | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ |
| 237 | | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ |
| 238 | | CSOR_NAND_RAL_3 /* RAL = 3Byes */ \ |
| 239 | | CSOR_NAND_PGS_4K /* Page Size = 4K */ \ |
| 240 | | CSOR_NAND_SPRZ_224/* Spare size = 224 */ \ |
| 241 | | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/ |
| 242 | |
| 243 | #define CONFIG_SYS_NAND_ONFI_DETECTION |
| 244 | |
| 245 | /* ONFI NAND Flash mode0 Timing Params */ |
| 246 | #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \ |
| 247 | FTIM0_NAND_TWP(0x18) | \ |
| 248 | FTIM0_NAND_TWCHT(0x07) | \ |
| 249 | FTIM0_NAND_TWH(0x0a)) |
| 250 | #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \ |
| 251 | FTIM1_NAND_TWBE(0x39) | \ |
| 252 | FTIM1_NAND_TRR(0x0e) | \ |
| 253 | FTIM1_NAND_TRP(0x18)) |
| 254 | #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \ |
| 255 | FTIM2_NAND_TREH(0x0a) | \ |
| 256 | FTIM2_NAND_TWHRE(0x1e)) |
| 257 | #define CONFIG_SYS_NAND_FTIM3 0x0 |
| 258 | |
| 259 | #define CONFIG_SYS_NAND_DDR_LAW 11 |
| 260 | #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } |
| 261 | #define CONFIG_SYS_MAX_NAND_DEVICE 1 |
| 262 | #define CONFIG_MTD_NAND_VERIFY_WRITE |
| 263 | #define CONFIG_CMD_NAND |
| 264 | |
| 265 | #define CONFIG_SYS_NAND_BLOCK_SIZE (512 * 1024) |
| 266 | |
| 267 | #if defined(CONFIG_NAND) |
| 268 | #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT |
| 269 | #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR |
| 270 | #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK |
| 271 | #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR |
| 272 | #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0 |
| 273 | #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1 |
| 274 | #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2 |
| 275 | #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3 |
| 276 | #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR_CSPR_EXT |
| 277 | #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR_CSPR |
| 278 | #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK |
| 279 | #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR |
| 280 | #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 |
| 281 | #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 |
| 282 | #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 |
| 283 | #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 |
| 284 | #else |
| 285 | #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR_CSPR_EXT |
| 286 | #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR_CSPR |
| 287 | #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK |
| 288 | #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR |
| 289 | #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 |
| 290 | #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 |
| 291 | #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 |
| 292 | #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 |
| 293 | #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NAND_CSPR_EXT |
| 294 | #define CONFIG_SYS_CSPR1 CONFIG_SYS_NAND_CSPR |
| 295 | #define CONFIG_SYS_AMASK1 CONFIG_SYS_NAND_AMASK |
| 296 | #define CONFIG_SYS_CSOR1 CONFIG_SYS_NAND_CSOR |
| 297 | #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NAND_FTIM0 |
| 298 | #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NAND_FTIM1 |
| 299 | #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NAND_FTIM2 |
| 300 | #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NAND_FTIM3 |
| 301 | #endif |
| 302 | |
| 303 | #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE |
| 304 | |
| 305 | #if defined(CONFIG_RAMBOOT_PBL) |
| 306 | #define CONFIG_SYS_RAMBOOT |
| 307 | #endif |
| 308 | |
| 309 | #define CONFIG_BOARD_EARLY_INIT_R |
| 310 | #define CONFIG_MISC_INIT_R |
| 311 | |
| 312 | #define CONFIG_HWCONFIG |
| 313 | |
| 314 | /* define to use L1 as initial stack */ |
| 315 | #define CONFIG_L1_INIT_RAM |
| 316 | #define CONFIG_SYS_INIT_RAM_LOCK |
| 317 | #define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */ |
| 318 | #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf |
| 319 | #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe0ec000 |
| 320 | /* The assembler doesn't like typecast */ |
| 321 | #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \ |
| 322 | ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \ |
| 323 | CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW) |
| 324 | #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 |
| 325 | |
| 326 | #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ |
| 327 | GENERATED_GBL_DATA_SIZE) |
| 328 | #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET |
| 329 | |
| 330 | #define CONFIG_SYS_MONITOR_LEN (512 * 1024) |
| 331 | #define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024) |
| 332 | |
| 333 | /* Serial Port - controlled on board with jumper J8 |
| 334 | * open - index 2 |
| 335 | * shorted - index 1 |
| 336 | */ |
| 337 | #define CONFIG_CONS_INDEX 1 |
| 338 | #define CONFIG_SYS_NS16550 |
| 339 | #define CONFIG_SYS_NS16550_SERIAL |
| 340 | #define CONFIG_SYS_NS16550_REG_SIZE 1 |
| 341 | #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2) |
| 342 | |
| 343 | #define CONFIG_SYS_BAUDRATE_TABLE \ |
| 344 | {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} |
| 345 | |
| 346 | #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500) |
| 347 | #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600) |
| 348 | #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500) |
| 349 | #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600) |
| 350 | #define CONFIG_SERIAL_MULTI /* Enable both serial ports */ |
| 351 | #define CONFIG_SYS_CONSOLE_IS_IN_ENV /* determine from environment */ |
| 352 | |
| 353 | /* Use the HUSH parser */ |
| 354 | #define CONFIG_SYS_HUSH_PARSER |
| 355 | #define CONFIG_SYS_PROMPT_HUSH_PS2 "> " |
| 356 | |
| 357 | /* pass open firmware flat tree */ |
| 358 | #define CONFIG_OF_LIBFDT |
| 359 | #define CONFIG_OF_BOARD_SETUP |
| 360 | #define CONFIG_OF_STDOUT_VIA_ALIAS |
| 361 | |
| 362 | /* new uImage format support */ |
| 363 | #define CONFIG_FIT |
| 364 | #define CONFIG_FIT_VERBOSE /* enable fit_format_{error,warning}() */ |
| 365 | |
| 366 | /* I2C */ |
| 367 | #define CONFIG_SYS_I2C |
| 368 | #define CONFIG_SYS_I2C_FSL /* Use FSL common I2C driver */ |
| 369 | #define CONFIG_SYS_FSL_I2C_SPEED 400000 /* I2C speed in Hz */ |
| 370 | #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F |
| 371 | #define CONFIG_SYS_FSL_I2C2_SPEED 400000 /* I2C speed in Hz */ |
| 372 | #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F |
| 373 | #define CONFIG_SYS_FSL_I2C_OFFSET 0x118000 |
| 374 | #define CONFIG_SYS_FSL_I2C2_OFFSET 0x119000 |
| 375 | |
| 376 | /* I2C bus multiplexer */ |
| 377 | #define I2C_MUX_PCA_ADDR 0x70 |
| 378 | |
| 379 | /* |
| 380 | * RTC configuration |
| 381 | */ |
| 382 | #define RTC |
| 383 | #define CONFIG_RTC_DS1337 1 |
| 384 | #define CONFIG_SYS_I2C_RTC_ADDR 0x68 |
| 385 | |
| 386 | /*DVI encoder*/ |
| 387 | #define CONFIG_HDMI_ENCODER_I2C_ADDR 0x75 |
| 388 | |
| 389 | /* |
| 390 | * eSPI - Enhanced SPI |
| 391 | */ |
| 392 | #define CONFIG_FSL_ESPI |
| 393 | #define CONFIG_SPI_FLASH |
| 394 | #define CONFIG_SPI_FLASH_STMICRO |
| 395 | #define CONFIG_CMD_SF |
| 396 | #define CONFIG_SF_DEFAULT_SPEED 10000000 |
| 397 | #define CONFIG_SF_DEFAULT_MODE 0 |
| 398 | |
| 399 | /* |
| 400 | * General PCI |
| 401 | * Memory space is mapped 1-1, but I/O space must start from 0. |
| 402 | */ |
| 403 | |
| 404 | #ifdef CONFIG_PCI |
| 405 | /* controller 1, direct to uli, tgtid 3, Base address 20000 */ |
| 406 | #ifdef CONFIG_PCIE1 |
| 407 | #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 |
| 408 | #define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000 |
| 409 | #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull |
| 410 | #define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000 /* 256M */ |
| 411 | #define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000 |
| 412 | #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 |
| 413 | #define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull |
| 414 | #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ |
| 415 | #endif |
| 416 | |
| 417 | /* controller 2, Slot 2, tgtid 2, Base address 201000 */ |
| 418 | #ifdef CONFIG_PCIE2 |
| 419 | #define CONFIG_SYS_PCIE2_MEM_VIRT 0x90000000 |
| 420 | #define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000 |
| 421 | #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc10000000ull |
| 422 | #define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000 /* 256M */ |
| 423 | #define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000 |
| 424 | #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 |
| 425 | #define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull |
| 426 | #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ |
| 427 | #endif |
| 428 | |
| 429 | /* controller 3, Slot 1, tgtid 1, Base address 202000 */ |
| 430 | #ifdef CONFIG_PCIE3 |
| 431 | #define CONFIG_SYS_PCIE3_MEM_VIRT 0xa0000000 |
| 432 | #define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000 |
| 433 | #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc20000000ull |
| 434 | #define CONFIG_SYS_PCIE3_MEM_SIZE 0x10000000 /* 256M */ |
| 435 | #define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000 |
| 436 | #define CONFIG_SYS_PCIE3_IO_BUS 0x00000000 |
| 437 | #define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull |
| 438 | #define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */ |
| 439 | #endif |
| 440 | |
| 441 | /* controller 4, Base address 203000 */ |
| 442 | #ifdef CONFIG_PCIE4 |
| 443 | #define CONFIG_SYS_PCIE4_MEM_VIRT 0xb0000000 |
| 444 | #define CONFIG_SYS_PCIE4_MEM_BUS 0xe0000000 |
| 445 | #define CONFIG_SYS_PCIE4_MEM_PHYS 0xc30000000ull |
| 446 | #define CONFIG_SYS_PCIE4_MEM_SIZE 0x10000000 /* 256M */ |
| 447 | #define CONFIG_SYS_PCIE4_IO_VIRT 0xf8030000 |
| 448 | #define CONFIG_SYS_PCIE4_IO_BUS 0x00000000 |
| 449 | #define CONFIG_SYS_PCIE4_IO_PHYS 0xff8030000ull |
| 450 | #define CONFIG_SYS_PCIE4_IO_SIZE 0x00010000 /* 64k */ |
| 451 | #endif |
| 452 | |
| 453 | #define CONFIG_PCI_PNP /* do pci plug-and-play */ |
| 454 | #define CONFIG_E1000 |
| 455 | |
| 456 | #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ |
| 457 | #define CONFIG_DOS_PARTITION |
| 458 | #endif /* CONFIG_PCI */ |
| 459 | |
| 460 | /* SATA */ |
| 461 | #define CONFIG_FSL_SATA_V2 |
| 462 | #ifdef CONFIG_FSL_SATA_V2 |
| 463 | #define CONFIG_LIBATA |
| 464 | #define CONFIG_FSL_SATA |
| 465 | |
| 466 | #define CONFIG_SYS_SATA_MAX_DEVICE 1 |
| 467 | #define CONFIG_SATA1 |
| 468 | #define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR |
| 469 | #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA |
| 470 | |
| 471 | #define CONFIG_LBA48 |
| 472 | #define CONFIG_CMD_SATA |
| 473 | #define CONFIG_DOS_PARTITION |
| 474 | #define CONFIG_CMD_EXT2 |
| 475 | #endif |
| 476 | |
| 477 | /* |
| 478 | * USB |
| 479 | */ |
| 480 | #define CONFIG_HAS_FSL_DR_USB |
| 481 | |
| 482 | #ifdef CONFIG_HAS_FSL_DR_USB |
| 483 | #define CONFIG_USB_EHCI |
| 484 | |
| 485 | #ifdef CONFIG_USB_EHCI |
| 486 | #define CONFIG_CMD_USB |
| 487 | #define CONFIG_USB_STORAGE |
| 488 | #define CONFIG_USB_EHCI_FSL |
| 489 | #define CONFIG_EHCI_HCD_INIT_AFTER_RESET |
| 490 | #define CONFIG_CMD_EXT2 |
| 491 | #endif |
| 492 | #endif |
| 493 | |
| 494 | #define CONFIG_MMC |
| 495 | |
| 496 | #ifdef CONFIG_MMC |
| 497 | #define CONFIG_FSL_ESDHC |
| 498 | #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR |
| 499 | #define CONFIG_CMD_MMC |
| 500 | #define CONFIG_GENERIC_MMC |
| 501 | #define CONFIG_CMD_EXT2 |
| 502 | #define CONFIG_CMD_FAT |
| 503 | #define CONFIG_DOS_PARTITION |
| 504 | #endif |
| 505 | |
| 506 | /* Qman/Bman */ |
| 507 | #ifndef CONFIG_NOBQFMAN |
| 508 | #define CONFIG_SYS_DPAA_QBMAN /* Support Q/Bman */ |
| 509 | #define CONFIG_SYS_BMAN_NUM_PORTALS 25 |
| 510 | #define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000 |
| 511 | #define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull |
| 512 | #define CONFIG_SYS_BMAN_MEM_SIZE 0x02000000 |
| 513 | #define CONFIG_SYS_QMAN_NUM_PORTALS 25 |
| 514 | #define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000 |
| 515 | #define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull |
| 516 | #define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000 |
| 517 | |
| 518 | #define CONFIG_SYS_DPAA_FMAN |
| 519 | #define CONFIG_SYS_DPAA_PME |
| 520 | |
| 521 | /* Default address of microcode for the Linux Fman driver */ |
| 522 | #if defined(CONFIG_SPIFLASH) |
| 523 | /* |
| 524 | * env is stored at 0x100000, sector size is 0x10000, ucode is stored after |
| 525 | * env, so we got 0x110000. |
| 526 | */ |
| 527 | #define CONFIG_SYS_QE_FW_IN_SPIFLASH |
| 528 | #define CONFIG_SYS_QE_FMAN_FW_ADDR 0x110000 |
| 529 | #elif defined(CONFIG_SDCARD) |
| 530 | /* |
| 531 | * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is |
Prabhakar Kushwaha | f203656 | 2014-01-14 11:34:26 +0530 | [diff] [blame^] | 532 | * about 825KB (1650 blocks), Env is stored after the image, and the env size is |
| 533 | * 0x2000 (16 blocks), 8 + 1650 + 16 = 1674, enlarge it to 1680. |
Priyanka Jain | c42c989 | 2013-10-18 17:19:23 +0530 | [diff] [blame] | 534 | */ |
| 535 | #define CONFIG_SYS_QE_FMAN_FW_IN_MMC |
Prabhakar Kushwaha | f203656 | 2014-01-14 11:34:26 +0530 | [diff] [blame^] | 536 | #define CONFIG_SYS_QE_FMAN_FW_ADDR (512 * 1680) |
Priyanka Jain | c42c989 | 2013-10-18 17:19:23 +0530 | [diff] [blame] | 537 | #elif defined(CONFIG_NAND) |
| 538 | #define CONFIG_SYS_QE_FMAN_FW_IN_NAND |
Prabhakar Kushwaha | f203656 | 2014-01-14 11:34:26 +0530 | [diff] [blame^] | 539 | #define CONFIG_SYS_QE_FMAN_FW_ADDR (4 * CONFIG_SYS_NAND_BLOCK_SIZE) |
Priyanka Jain | c42c989 | 2013-10-18 17:19:23 +0530 | [diff] [blame] | 540 | #else |
| 541 | #define CONFIG_SYS_QE_FMAN_FW_IN_NOR |
Prabhakar Kushwaha | f203656 | 2014-01-14 11:34:26 +0530 | [diff] [blame^] | 542 | #define CONFIG_SYS_QE_FMAN_FW_ADDR 0xEFF00000 |
Priyanka Jain | c42c989 | 2013-10-18 17:19:23 +0530 | [diff] [blame] | 543 | #endif |
| 544 | #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000 |
| 545 | #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH) |
| 546 | #endif /* CONFIG_NOBQFMAN */ |
| 547 | |
| 548 | #ifdef CONFIG_SYS_DPAA_FMAN |
| 549 | #define CONFIG_FMAN_ENET |
| 550 | #define CONFIG_PHY_VITESSE |
| 551 | #define CONFIG_PHY_REALTEK |
| 552 | #endif |
| 553 | |
| 554 | #ifdef CONFIG_FMAN_ENET |
| 555 | #define CONFIG_MII /* MII PHY management */ |
| 556 | #define CONFIG_ETHPRIME "FM1@DTSEC1" |
| 557 | #define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */ |
| 558 | #endif |
| 559 | |
| 560 | /* |
| 561 | * Environment |
| 562 | */ |
| 563 | #define CONFIG_LOADS_ECHO /* echo on for serial download */ |
| 564 | #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */ |
| 565 | |
| 566 | /* |
| 567 | * Command line configuration. |
| 568 | */ |
| 569 | #include <config_cmd_default.h> |
| 570 | |
| 571 | #define CONFIG_CMD_DATE |
| 572 | #define CONFIG_CMD_DHCP |
| 573 | #define CONFIG_CMD_ELF |
| 574 | #define CONFIG_CMD_ERRATA |
| 575 | #define CONFIG_CMD_GREPENV |
| 576 | #define CONFIG_CMD_IRQ |
| 577 | #define CONFIG_CMD_I2C |
| 578 | #define CONFIG_CMD_MII |
| 579 | #define CONFIG_CMD_PING |
| 580 | #define CONFIG_CMD_REGINFO |
| 581 | #define CONFIG_CMD_SETEXPR |
| 582 | |
| 583 | #ifdef CONFIG_PCI |
| 584 | #define CONFIG_CMD_PCI |
| 585 | #define CONFIG_CMD_NET |
| 586 | #endif |
| 587 | |
| 588 | /* |
| 589 | * Miscellaneous configurable options |
| 590 | */ |
| 591 | #define CONFIG_SYS_LONGHELP /* undef to save memory */ |
| 592 | #define CONFIG_CMDLINE_EDITING /* Command-line editing */ |
| 593 | #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ |
| 594 | #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ |
| 595 | #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ |
| 596 | #ifdef CONFIG_CMD_KGDB |
| 597 | #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ |
| 598 | #else |
| 599 | #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ |
| 600 | #endif |
| 601 | #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) |
| 602 | #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ |
| 603 | #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */ |
| 604 | #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks*/ |
| 605 | |
| 606 | /* |
| 607 | * For booting Linux, the board info and command line data |
| 608 | * have to be in the first 64 MB of memory, since this is |
| 609 | * the maximum mapped by the Linux kernel during initialization. |
| 610 | */ |
| 611 | #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/ |
| 612 | #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ |
| 613 | |
| 614 | #ifdef CONFIG_CMD_KGDB |
| 615 | #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ |
Priyanka Jain | c42c989 | 2013-10-18 17:19:23 +0530 | [diff] [blame] | 616 | #endif |
| 617 | |
| 618 | /* |
| 619 | * Environment Configuration |
| 620 | */ |
| 621 | #define CONFIG_ROOTPATH "/opt/nfsroot" |
| 622 | #define CONFIG_BOOTFILE "uImage" |
| 623 | #define CONFIG_UBOOTPATH "u-boot.bin" /* U-Boot image on TFTP server*/ |
| 624 | |
| 625 | /* default location for tftp and bootm */ |
| 626 | #define CONFIG_LOADADDR 1000000 |
| 627 | |
| 628 | #define CONFIG_BOOTDELAY 10 /*-1 disables auto-boot*/ |
| 629 | |
| 630 | #define CONFIG_BAUDRATE 115200 |
| 631 | |
| 632 | #define __USB_PHY_TYPE utmi |
| 633 | |
| 634 | #define CONFIG_EXTRA_ENV_SETTINGS \ |
| 635 | "hwconfig=fsl_ddr:ctlr_intlv=cacheline," \ |
| 636 | "bank_intlv=cs0_cs1;" \ |
| 637 | "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\ |
| 638 | "netdev=eth0\0" \ |
| 639 | "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ |
| 640 | "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \ |
| 641 | "tftpflash=tftpboot $loadaddr $uboot && " \ |
| 642 | "protect off $ubootaddr +$filesize && " \ |
| 643 | "erase $ubootaddr +$filesize && " \ |
| 644 | "cp.b $loadaddr $ubootaddr $filesize && " \ |
| 645 | "protect on $ubootaddr +$filesize && " \ |
| 646 | "cmp.b $loadaddr $ubootaddr $filesize\0" \ |
| 647 | "consoledev=ttyS0\0" \ |
| 648 | "ramdiskaddr=2000000\0" \ |
| 649 | "ramdiskfile=t1040rdb_pi/ramdisk.uboot\0" \ |
| 650 | "fdtaddr=c00000\0" \ |
| 651 | "fdtfile=t1040rdb_pi/t1040rdb_pi.dtb\0" \ |
| 652 | "bdev=sda3\0" \ |
| 653 | "c=ffe\0" |
| 654 | |
| 655 | #define CONFIG_LINUX \ |
| 656 | "setenv bootargs root=/dev/ram rw " \ |
| 657 | "console=$consoledev,$baudrate $othbootargs;" \ |
| 658 | "setenv ramdiskaddr 0x02000000;" \ |
| 659 | "setenv fdtaddr 0x00c00000;" \ |
| 660 | "setenv loadaddr 0x1000000;" \ |
| 661 | "bootm $loadaddr $ramdiskaddr $fdtaddr" |
| 662 | |
| 663 | #define CONFIG_HDBOOT \ |
| 664 | "setenv bootargs root=/dev/$bdev rw " \ |
| 665 | "console=$consoledev,$baudrate $othbootargs;" \ |
| 666 | "tftp $loadaddr $bootfile;" \ |
| 667 | "tftp $fdtaddr $fdtfile;" \ |
| 668 | "bootm $loadaddr - $fdtaddr" |
| 669 | |
| 670 | #define CONFIG_NFSBOOTCOMMAND \ |
| 671 | "setenv bootargs root=/dev/nfs rw " \ |
| 672 | "nfsroot=$serverip:$rootpath " \ |
| 673 | "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ |
| 674 | "console=$consoledev,$baudrate $othbootargs;" \ |
| 675 | "tftp $loadaddr $bootfile;" \ |
| 676 | "tftp $fdtaddr $fdtfile;" \ |
| 677 | "bootm $loadaddr - $fdtaddr" |
| 678 | |
| 679 | #define CONFIG_RAMBOOTCOMMAND \ |
| 680 | "setenv bootargs root=/dev/ram rw " \ |
| 681 | "console=$consoledev,$baudrate $othbootargs;" \ |
| 682 | "tftp $ramdiskaddr $ramdiskfile;" \ |
| 683 | "tftp $loadaddr $bootfile;" \ |
| 684 | "tftp $fdtaddr $fdtfile;" \ |
| 685 | "bootm $loadaddr $ramdiskaddr $fdtaddr" |
| 686 | |
| 687 | #define CONFIG_BOOTCOMMAND CONFIG_LINUX |
| 688 | |
| 689 | #ifdef CONFIG_SECURE_BOOT |
| 690 | #include <asm/fsl_secure_boot.h> |
| 691 | #endif |
| 692 | |
| 693 | #endif /* __CONFIG_H */ |