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git01.mediatek.com / filogic / uboot / f1fc77cc3b666ef2d44118815acd2b720cbf9d4a / . / arch / powerpc / include / asm / global_data.h
blob: 90bf5a2aea5df571e0657ea3dff66972c6974339 [file] [log] [blame]
Tom Rini10e47792018-05-06 17:58:06 -0400[diff] [blame]1/* SPDX-License-Identifier: GPL-2.0+ */
wdenk0157ced2002-10-21 17:04:47 +0000[diff] [blame]2/*
Wolfgang Denkf710efd2010-07-24 20:22:02 +0200[diff] [blame]3 * (C) Copyright 2002-2010
Yangbo Luff98fde2020-06-17 18:08:57 +0800[diff] [blame]4 * Copyright 2020 NXP
wdenk0157ced2002-10-21 17:04:47 +0000[diff] [blame]5 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
wdenk0157ced2002-10-21 17:04:47 +0000[diff] [blame]6 */
7
8#ifndef __ASM_GBL_DATA_H
9#define __ASM_GBL_DATA_H
Eran Liberty9095d4a2005-07-28 10:08:46 -0500[diff] [blame]10
Tom Rinif1fc77c2021-06-03 09:38:59 -0400[diff] [blame^]11#include <config.h>
Eran Liberty9095d4a2005-07-28 10:08:46 -0500[diff] [blame]12#include "asm/types.h"
13
Simon Glass3ac47d72012-12-13 20:48:30 +0000[diff] [blame]14/* Architecture-specific global data */
15struct arch_global_data {
Simon Glass9e247d12012-12-13 20:49:05 +0000[diff] [blame]16#if defined(CONFIG_FSL_ESDHC)
17 u32 sdhc_clk;
Yangbo Lu0fa68762019-12-19 18:59:28 +0800[diff] [blame]18 u32 sdhc_per_clk;
Simon Glass9e247d12012-12-13 20:49:05 +0000[diff] [blame]19#endif
Christophe Leroyb3510fb2018-03-16 17:20:41 +0100[diff] [blame]20#if defined(CONFIG_MPC8xx)
Christophe Leroy069fa832017-07-06 10:23:22 +0200[diff] [blame]21 unsigned long brg_clk;
22#endif
Simon Glass34a194f2012-12-13 20:48:44 +0000[diff] [blame]23#if defined(CONFIG_CPM2)
Simon Glass44ea8512012-12-13 20:48:46 +0000[diff] [blame]24 /* There are many clocks on the MPC8260 - see page 9-5 */
25 unsigned long vco_out;
26 unsigned long cpm_clk;
27 unsigned long scc_clk;
Simon Glass34a194f2012-12-13 20:48:44 +0000[diff] [blame]28 unsigned long brg_clk;
29#endif
Simon Glasscc76e9e2012-12-13 20:48:47 +0000[diff] [blame]30 /* TODO: sjg@chromium.org: Should these be unslgned long? */
Peter Tyser62e73982009-05-22 17:23:24 -0500[diff] [blame]31#if defined(CONFIG_MPC83xx)
Mario Six7cab1472018-08-06 10:23:36 +0200[diff] [blame]32#ifdef CONFIG_CLK_MPC83XX
33 u32 core_clk;
34#else
Eran Liberty9095d4a2005-07-28 10:08:46 -0500[diff] [blame]35 /* There are other clocks in the MPC83XX */
36 u32 csb_clk;
Mario Six9164bdd2019-01-21 09:17:25 +0100[diff] [blame]37# if defined(CONFIG_ARCH_MPC8308) || defined(CONFIG_ARCH_MPC831X) || \
Mario Six60b11232019-01-21 09:17:29 +0100[diff] [blame]38 defined(CONFIG_ARCH_MPC834X) || defined(CONFIG_ARCH_MPC837X)
Eran Liberty9095d4a2005-07-28 10:08:46 -0500[diff] [blame]39 u32 tsec1_clk;
40 u32 tsec2_clk;
Eran Liberty9095d4a2005-07-28 10:08:46 -0500[diff] [blame]41 u32 usbdr_clk;
Mario Sixb2e701c2019-01-21 09:17:24 +0100[diff] [blame]42# elif defined(CONFIG_ARCH_MPC8309)
Gerlando Falautofe201cb2012-10-10 22:13:08 +0000[diff] [blame]43 u32 usbdr_clk;
Simon Glasscc76e9e2012-12-13 20:48:47 +0000[diff] [blame]44# endif
Mario Six0344f5e2019-01-21 09:17:27 +0100[diff] [blame]45# if defined(CONFIG_ARCH_MPC834X)
Scott Woodbeb638a2007-04-16 14:34:18 -0500[diff] [blame]46 u32 usbmph_clk;
Mario Six0344f5e2019-01-21 09:17:27 +0100[diff] [blame]47# endif /* CONFIG_ARCH_MPC834X */
Mario Six9164bdd2019-01-21 09:17:25 +0100[diff] [blame]48# if defined(CONFIG_ARCH_MPC8315)
Dave Liue0cfec82007-09-18 12:36:58 +0800[diff] [blame]49 u32 tdm_clk;
Simon Glasscc76e9e2012-12-13 20:48:47 +0000[diff] [blame]50# endif
Dave Liua46daea2006-11-03 19:33:44 -0600[diff] [blame]51 u32 core_clk;
Eran Liberty9095d4a2005-07-28 10:08:46 -0500[diff] [blame]52 u32 enc_clk;
53 u32 lbiu_clk;
54 u32 lclk_clk;
Mario Six9164bdd2019-01-21 09:17:25 +0100[diff] [blame]55# if defined(CONFIG_ARCH_MPC8308) || defined(CONFIG_ARCH_MPC831X) || \
Mario Six60b11232019-01-21 09:17:29 +0100[diff] [blame]56 defined(CONFIG_ARCH_MPC837X)
Dave Liu5245ff52007-09-18 12:36:11 +0800[diff] [blame]57 u32 pciexp1_clk;
58 u32 pciexp2_clk;
Simon Glasscc76e9e2012-12-13 20:48:47 +0000[diff] [blame]59# endif
Mario Six60b11232019-01-21 09:17:29 +0100[diff] [blame]60# if defined(CONFIG_ARCH_MPC837X) || defined(CONFIG_ARCH_MPC8315)
Dave Liu5245ff52007-09-18 12:36:11 +0800[diff] [blame]61 u32 sata_clk;
Simon Glasscc76e9e2012-12-13 20:48:47 +0000[diff] [blame]62# endif
Mario Six84eb4312019-01-21 09:17:28 +0100[diff] [blame]63# if defined(CONFIG_ARCH_MPC8360)
Simon Glasscc76e9e2012-12-13 20:48:47 +0000[diff] [blame]64 u32 mem_sec_clk;
Mario Six84eb4312019-01-21 09:17:28 +0100[diff] [blame]65# endif /* CONFIG_ARCH_MPC8360 */
Dave Liu5245ff52007-09-18 12:36:11 +0800[diff] [blame]66#endif
Mario Six7cab1472018-08-06 10:23:36 +0200[diff] [blame]67#endif
Simon Glassa8b57392012-12-13 20:48:48 +0000[diff] [blame]68#if defined(CONFIG_MPC85xx) || defined(CONFIG_MPC86xx)
69 u32 lbc_clk;
70 void *cpu;
71#endif /* CONFIG_MPC85xx || CONFIG_MPC86xx */
Simon Glassc2baaec2012-12-13 20:48:49 +0000[diff] [blame]72#if defined(CONFIG_MPC83xx) || defined(CONFIG_MPC85xx) || \
73 defined(CONFIG_MPC86xx)
74 u32 i2c1_clk;
75 u32 i2c2_clk;
76#endif
Simon Glass8518b172012-12-13 20:48:50 +0000[diff] [blame]77#if defined(CONFIG_QE)
78 u32 qe_clk;
79 u32 brg_clk;
80 uint mp_alloc_base;
81 uint mp_alloc_top;
82#endif /* CONFIG_QE */
Simon Glassc6622d62012-12-13 20:48:51 +0000[diff] [blame]83#if defined(CONFIG_FSL_LAW)
84 u32 used_laws;
85#endif
Simon Glass0b466582012-12-13 20:48:52 +0000[diff] [blame]86#if defined(CONFIG_E500)
87 u32 used_tlb_cams[(CONFIG_SYS_NUM_TLBCAMS+31)/32];
88#endif
Simon Glass4d6eaa32012-12-13 20:48:56 +0000[diff] [blame]89 unsigned long reset_status; /* reset status register at boot */
Simon Glass387a1f22012-12-13 20:48:57 +0000[diff] [blame]90#if defined(CONFIG_MPC83xx)
91 unsigned long arbiter_event_attributes;
92 unsigned long arbiter_event_address;
93#endif
Simon Glass89370732017-01-23 13:31:23 -0700[diff] [blame]94#if defined(CONFIG_CPM2)
Simon Glass93980082012-12-13 20:48:58 +0000[diff] [blame]95 unsigned int dp_alloc_base;
96 unsigned int dp_alloc_top;
97#endif
Simon Glassf2d9aaf2012-12-13 20:49:02 +0000[diff] [blame]98#ifdef CONFIG_SYS_FPGA_COUNT
99 unsigned fpga_state[CONFIG_SYS_FPGA_COUNT];
100#endif
Stefan Roeseb47a63d2015-10-02 08:20:35 +0200[diff] [blame]101#if defined(CONFIG_WD_MAX_RATE)
102 unsigned long long wdt_last; /* trace watch-dog triggering rate */
103#endif
104#if defined(CONFIG_LWMON5)
105 unsigned long kbd_status;
106#endif
Simon Glasscc76e9e2012-12-13 20:48:47 +0000[diff] [blame]107};
108
Simon Glass1c62cc22012-12-13 20:49:23 +0000[diff] [blame]109#include <asm-generic/global_data.h>
wdenk0157ced2002-10-21 17:04:47 +0000[diff] [blame]110
111#if 1
Wolfgang Denk69c09642008-02-14 22:43:22 +0100[diff] [blame]112#define DECLARE_GLOBAL_DATA_PTR register volatile gd_t *gd asm ("r2")
wdenk0157ced2002-10-21 17:04:47 +0000[diff] [blame]113#else /* We could use plain global data, but the resulting code is bigger */
114#define XTRN_DECLARE_GLOBAL_DATA_PTR extern
115#define DECLARE_GLOBAL_DATA_PTR XTRN_DECLARE_GLOBAL_DATA_PTR \
116 gd_t *gd
117#endif
118
119#endif /* __ASM_GBL_DATA_H */