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Tom Warrenc47e7172013-01-28 13:32:07 +00001/*
2 * Copyright (c) 2010-2013, NVIDIA CORPORATION. All rights reserved.
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
11 * more details.
12 *
13 * You should have received a copy of the GNU General Public License
14 * along with this program. If not, see <http://www.gnu.org/licenses/>.
15 */
16
17/* Tegra114 clock PLL tables */
18
19#ifndef _TEGRA114_CLOCK_TABLES_H_
20#define _TEGRA114_CLOCK_TABLES_H_
21
22/* The PLLs supported by the hardware */
23enum clock_id {
24 CLOCK_ID_FIRST,
25 CLOCK_ID_CGENERAL = CLOCK_ID_FIRST,
26 CLOCK_ID_MEMORY,
27 CLOCK_ID_PERIPH,
28 CLOCK_ID_AUDIO,
29 CLOCK_ID_USB,
30 CLOCK_ID_DISPLAY,
31
32 /* now the simple ones */
33 CLOCK_ID_FIRST_SIMPLE,
34 CLOCK_ID_XCPU = CLOCK_ID_FIRST_SIMPLE,
35 CLOCK_ID_EPCI,
36 CLOCK_ID_SFROM32KHZ,
37
38 /* These are the base clocks (inputs to the Tegra SOC) */
39 CLOCK_ID_32KHZ,
40 CLOCK_ID_OSC,
41
42 CLOCK_ID_COUNT, /* number of PLLs */
43 CLOCK_ID_DISPLAY2, /* placeholder */
44 CLOCK_ID_NONE = -1,
45};
46
47/* The clocks supported by the hardware */
48enum periph_id {
49 PERIPH_ID_FIRST,
50
51 /* Low word: 31:0 (DEVICES_L) */
52 PERIPH_ID_CPU = PERIPH_ID_FIRST,
53 PERIPH_ID_COP,
54 PERIPH_ID_TRIGSYS,
55 PERIPH_ID_RESERVED3,
56 PERIPH_ID_RTC,
57 PERIPH_ID_TMR,
58 PERIPH_ID_UART1,
59 PERIPH_ID_UART2,
60
61 /* 8 */
62 PERIPH_ID_GPIO,
63 PERIPH_ID_SDMMC2,
64 PERIPH_ID_SPDIF,
65 PERIPH_ID_I2S1,
66 PERIPH_ID_I2C1,
67 PERIPH_ID_NDFLASH,
68 PERIPH_ID_SDMMC1,
69 PERIPH_ID_SDMMC4,
70
71 /* 16 */
72 PERIPH_ID_RESERVED16,
73 PERIPH_ID_PWM,
74 PERIPH_ID_I2S2,
75 PERIPH_ID_EPP,
76 PERIPH_ID_VI,
77 PERIPH_ID_2D,
78 PERIPH_ID_USBD,
79 PERIPH_ID_ISP,
80
81 /* 24 */
82 PERIPH_ID_3D,
83 PERIPH_ID_RESERVED24,
84 PERIPH_ID_DISP2,
85 PERIPH_ID_DISP1,
86 PERIPH_ID_HOST1X,
87 PERIPH_ID_VCP,
88 PERIPH_ID_I2S0,
89 PERIPH_ID_CACHE2,
90
91 /* Middle word: 63:32 (DEVICES_H) */
92 PERIPH_ID_MEM,
93 PERIPH_ID_AHBDMA,
94 PERIPH_ID_APBDMA,
95 PERIPH_ID_RESERVED35,
96 PERIPH_ID_KBC,
97 PERIPH_ID_STAT_MON,
98 PERIPH_ID_PMC,
99 PERIPH_ID_FUSE,
100
101 /* 40 */
102 PERIPH_ID_KFUSE,
103 PERIPH_ID_SBC1,
104 PERIPH_ID_SNOR,
105 PERIPH_ID_RESERVED43,
106 PERIPH_ID_SBC2,
107 PERIPH_ID_RESERVED45,
108 PERIPH_ID_SBC3,
109 PERIPH_ID_I2C5,
110
111 /* 48 */
112 PERIPH_ID_DSI,
113 PERIPH_ID_TVO,
114 PERIPH_ID_MIPI,
115 PERIPH_ID_HDMI,
116 PERIPH_ID_CSI,
117 PERIPH_ID_TVDAC,
118 PERIPH_ID_I2C2,
119 PERIPH_ID_UART3,
120
121 /* 56 */
122 PERIPH_ID_RESERVED56,
123 PERIPH_ID_EMC,
124 PERIPH_ID_USB2,
125 PERIPH_ID_USB3,
126 PERIPH_ID_MPE,
127 PERIPH_ID_VDE,
128 PERIPH_ID_BSEA,
129 PERIPH_ID_BSEV,
130
131 /* Upper word 95:64 (DEVICES_U) */
132 PERIPH_ID_SPEEDO,
133 PERIPH_ID_UART4,
134 PERIPH_ID_UART5,
135 PERIPH_ID_I2C3,
136 PERIPH_ID_SBC4,
137 PERIPH_ID_SDMMC3,
138 PERIPH_ID_PCIE,
139 PERIPH_ID_OWR,
140
141 /* 72 */
142 PERIPH_ID_AFI,
143 PERIPH_ID_CORESIGHT,
144 PERIPH_ID_PCIEXCLK,
145 PERIPH_ID_AVPUCQ,
146 PERIPH_ID_RESERVED76,
147 PERIPH_ID_RESERVED77,
148 PERIPH_ID_RESERVED78,
149 PERIPH_ID_DTV,
150
151 /* 80 */
152 PERIPH_ID_NANDSPEED,
153 PERIPH_ID_I2CSLOW,
154 PERIPH_ID_DSIB,
155 PERIPH_ID_RESERVED83,
156 PERIPH_ID_IRAMA,
157 PERIPH_ID_IRAMB,
158 PERIPH_ID_IRAMC,
159 PERIPH_ID_IRAMD,
160
161 /* 88 */
162 PERIPH_ID_CRAM2,
163 PERIPH_ID_RESERVED89,
164 PERIPH_ID_MDOUBLER,
165 PERIPH_ID_RESERVED91,
166 PERIPH_ID_SUSOUT,
167 PERIPH_ID_RESERVED93,
168 PERIPH_ID_RESERVED94,
169 PERIPH_ID_RESERVED95,
170
171 PERIPH_ID_VW_FIRST,
172 /* V word: 31:0 */
173 PERIPH_ID_CPUG = PERIPH_ID_VW_FIRST,
174 PERIPH_ID_CPULP,
175 PERIPH_ID_3D2,
176 PERIPH_ID_MSELECT,
177 PERIPH_ID_TSENSOR,
178 PERIPH_ID_I2S3,
179 PERIPH_ID_I2S4,
180 PERIPH_ID_I2C4,
181
182 /* 104 */
183 PERIPH_ID_SBC5,
184 PERIPH_ID_SBC6,
185 PERIPH_ID_AUDIO,
186 PERIPH_ID_APBIF,
187 PERIPH_ID_DAM0,
188 PERIPH_ID_DAM1,
189 PERIPH_ID_DAM2,
190 PERIPH_ID_HDA2CODEC2X,
191
192 /* 112 */
193 PERIPH_ID_ATOMICS,
194 PERIPH_ID_EX_RESERVED17,
195 PERIPH_ID_EX_RESERVED18,
196 PERIPH_ID_EX_RESERVED19,
197 PERIPH_ID_EX_RESERVED20,
198 PERIPH_ID_EX_RESERVED21,
199 PERIPH_ID_EX_RESERVED22,
200 PERIPH_ID_ACTMON,
201
202 /* 120 */
203 PERIPH_ID_EX_RESERVED24,
204 PERIPH_ID_EX_RESERVED25,
205 PERIPH_ID_EX_RESERVED26,
206 PERIPH_ID_EX_RESERVED27,
207 PERIPH_ID_SATA,
208 PERIPH_ID_HDA,
209 PERIPH_ID_EX_RESERVED30,
210 PERIPH_ID_EX_RESERVED31,
211
212 /* W word: 31:0 */
213 PERIPH_ID_HDA2HDMICODEC,
214 PERIPH_ID_RESERVED1_SATACOLD,
215 PERIPH_ID_RESERVED2_PCIERX0,
216 PERIPH_ID_RESERVED3_PCIERX1,
217 PERIPH_ID_RESERVED4_PCIERX2,
218 PERIPH_ID_RESERVED5_PCIERX3,
219 PERIPH_ID_RESERVED6_PCIERX4,
220 PERIPH_ID_RESERVED7_PCIERX5,
221
222 /* 136 */
223 PERIPH_ID_CEC,
224 PERIPH_ID_PCIE2_IOBIST,
225 PERIPH_ID_EMC_IOBIST,
226 PERIPH_ID_HDMI_IOBIST,
227 PERIPH_ID_SATA_IOBIST,
228 PERIPH_ID_MIPI_IOBIST,
229 PERIPH_ID_EMC1_IOBIST,
230 PERIPH_ID_XUSB,
231
232 /* 144 */
233 PERIPH_ID_CILAB,
234 PERIPH_ID_CILCD,
235 PERIPH_ID_CILE,
236 PERIPH_ID_DSIA_LP,
237 PERIPH_ID_DSIB_LP,
238 PERIPH_ID_RESERVED21_ENTROPY,
239 PERIPH_ID_RESERVED22_W,
240 PERIPH_ID_RESERVED23_W,
241
242 /* 152 */
243 PERIPH_ID_RESERVED24_W,
244 PERIPH_ID_AMX0,
245 PERIPH_ID_ADX0,
246 PERIPH_ID_DVFS,
247 PERIPH_ID_XUSB_SS,
248 PERIPH_ID_EMC_DLL,
249 PERIPH_ID_MC1,
250 PERIPH_ID_EMC1,
251
252 PERIPH_ID_COUNT,
253 PERIPH_ID_NONE = -1,
254};
255
256enum pll_out_id {
257 PLL_OUT1,
258 PLL_OUT2,
259 PLL_OUT3,
260 PLL_OUT4
261};
262
263/*
264 * Clock peripheral IDs which sadly don't match up with PERIPH_ID. we want
265 * callers to use the PERIPH_ID for all access to peripheral clocks to avoid
266 * confusion bewteen PERIPH_ID_... and PERIPHC_...
267 *
268 * We don't call this CLOCK_PERIPH_ID or PERIPH_CLOCK_ID as it would just be
269 * confusing.
270 */
271enum periphc_internal_id {
272 /* 0x00 */
273 PERIPHC_I2S1,
274 PERIPHC_I2S2,
275 PERIPHC_SPDIF_OUT,
276 PERIPHC_SPDIF_IN,
277 PERIPHC_PWM,
278 PERIPHC_05h,
279 PERIPHC_SBC2,
280 PERIPHC_SBC3,
281
282 /* 0x08 */
283 PERIPHC_08h,
284 PERIPHC_I2C1,
285 PERIPHC_I2C5,
286 PERIPHC_0bh,
287 PERIPHC_0ch,
288 PERIPHC_SBC1,
289 PERIPHC_DISP1,
290 PERIPHC_DISP2,
291
292 /* 0x10 */
293 PERIPHC_CVE,
294 PERIPHC_11h,
295 PERIPHC_VI,
296 PERIPHC_13h,
297 PERIPHC_SDMMC1,
298 PERIPHC_SDMMC2,
299 PERIPHC_G3D,
300 PERIPHC_G2D,
301
302 /* 0x18 */
303 PERIPHC_NDFLASH,
304 PERIPHC_SDMMC4,
305 PERIPHC_VFIR,
306 PERIPHC_EPP,
307 PERIPHC_MPE,
308 PERIPHC_MIPI,
309 PERIPHC_UART1,
310 PERIPHC_UART2,
311
312 /* 0x20 */
313 PERIPHC_HOST1X,
314 PERIPHC_21h,
315 PERIPHC_TVO,
316 PERIPHC_HDMI,
317 PERIPHC_24h,
318 PERIPHC_TVDAC,
319 PERIPHC_I2C2,
320 PERIPHC_EMC,
321
322 /* 0x28 */
323 PERIPHC_UART3,
324 PERIPHC_29h,
325 PERIPHC_VI_SENSOR,
326 PERIPHC_2bh,
327 PERIPHC_2ch,
328 PERIPHC_SBC4,
329 PERIPHC_I2C3,
330 PERIPHC_SDMMC3,
331
332 /* 0x30 */
333 PERIPHC_UART4,
334 PERIPHC_UART5,
335 PERIPHC_VDE,
336 PERIPHC_OWR,
337 PERIPHC_NOR,
338 PERIPHC_CSITE,
339 PERIPHC_I2S0,
340 PERIPHC_37h,
341
342 PERIPHC_VW_FIRST,
343 /* 0x38 */
344 PERIPHC_G3D2 = PERIPHC_VW_FIRST,
345 PERIPHC_MSELECT,
346 PERIPHC_TSENSOR,
347 PERIPHC_I2S3,
348 PERIPHC_I2S4,
349 PERIPHC_I2C4,
350 PERIPHC_SBC5,
351 PERIPHC_SBC6,
352
353 /* 0x40 */
354 PERIPHC_AUDIO,
355 PERIPHC_41h,
356 PERIPHC_DAM0,
357 PERIPHC_DAM1,
358 PERIPHC_DAM2,
359 PERIPHC_HDA2CODEC2X,
360 PERIPHC_ACTMON,
361 PERIPHC_EXTPERIPH1,
362
363 /* 0x48 */
364 PERIPHC_EXTPERIPH2,
365 PERIPHC_EXTPERIPH3,
366 PERIPHC_NANDSPEED,
367 PERIPHC_I2CSLOW,
368 PERIPHC_SYS,
369 PERIPHC_SPEEDO,
370 PERIPHC_4eh,
371 PERIPHC_4fh,
372
373 /* 0x50 */
374 PERIPHC_50h,
375 PERIPHC_51h,
376 PERIPHC_52h,
377 PERIPHC_53h,
378 PERIPHC_SATAOOB,
379 PERIPHC_SATA,
380 PERIPHC_HDA,
381
382 PERIPHC_COUNT,
383
384 PERIPHC_NONE = -1,
385};
386
387/* Converts a clock number to a clock register: 0=L, 1=H, 2=U, 0=V, 1=W */
388#define PERIPH_REG(id) \
389 (id < PERIPH_ID_VW_FIRST) ? \
390 ((id) >> 5) : ((id - PERIPH_ID_VW_FIRST) >> 5)
391
392/* Mask value for a clock (within PERIPH_REG(id)) */
393#define PERIPH_MASK(id) (1 << ((id) & 0x1f))
394
395/* return 1 if a PLL ID is in range */
396#define clock_id_is_pll(id) ((id) >= CLOCK_ID_FIRST && (id) < CLOCK_ID_COUNT)
397
398/* return 1 if a peripheral ID is in range */
399#define clock_periph_id_isvalid(id) ((id) >= PERIPH_ID_FIRST && \
400 (id) < PERIPH_ID_COUNT)
401
402#endif /* _TEGRA114_CLOCK_TABLES_H_ */