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Tom Rini10e47792018-05-06 17:58:06 -04001/* SPDX-License-Identifier: GPL-2.0+ */
Mingkai Hueee86ff2015-10-26 19:47:52 +08002/*
3 * Copyright 2015 Freescale Semiconductor
Mingkai Hueee86ff2015-10-26 19:47:52 +08004 */
5
6#ifndef __LS1043ARDB_H__
7#define __LS1043ARDB_H__
8
9#include "ls1043a_common.h"
10
Mingkai Hueee86ff2015-10-26 19:47:52 +080011#define CONFIG_LAYERSCAPE_NS_ACCESS
Mingkai Hueee86ff2015-10-26 19:47:52 +080012
13#define CONFIG_DIMM_SLOTS_PER_CTLR 1
14/* Physical Memory Map */
Mingkai Hueee86ff2015-10-26 19:47:52 +080015
16#define CONFIG_SYS_SPD_BUS_NUM 0
17
Hou Zhiqianga43c3ac2017-02-06 11:29:00 +080018#ifndef CONFIG_SPL
Mingkai Hueee86ff2015-10-26 19:47:52 +080019#define CONFIG_SYS_DDR_RAW_TIMING
Mingkai Hueee86ff2015-10-26 19:47:52 +080020#define CONFIG_MEM_INIT_VALUE 0xdeadbeef
York Sun9a577292017-09-28 08:42:13 -070021#endif
Mingkai Hueee86ff2015-10-26 19:47:52 +080022
Gong Qianyuf671f6c2015-10-26 19:47:56 +080023#ifdef CONFIG_SD_BOOT
York Sunf7eed6b2017-09-28 08:42:16 -070024#define CONFIG_SYS_SPL_ARGS_ADDR 0x90000000
York Sunf7eed6b2017-09-28 08:42:16 -070025#define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTOR 0x500
26#define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTORS 30
Gong Qianyuf671f6c2015-10-26 19:47:56 +080027#endif
28
Mingkai Hueee86ff2015-10-26 19:47:52 +080029/*
30 * NOR Flash Definitions
31 */
32#define CONFIG_SYS_NOR_CSPR_EXT (0x0)
33#define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024)
34#define CONFIG_SYS_NOR_CSPR \
35 (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
36 CSPR_PORT_SIZE_16 | \
37 CSPR_MSEL_NOR | \
38 CSPR_V)
39
40/* NOR Flash Timing Params */
41#define CONFIG_SYS_NOR_CSOR (CSOR_NOR_ADM_SHIFT(4) | \
42 CSOR_NOR_TRHZ_80)
43#define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x1) | \
44 FTIM0_NOR_TEADC(0x1) | \
45 FTIM0_NOR_TAVDS(0x0) | \
46 FTIM0_NOR_TEAHC(0xc))
47#define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x1c) | \
48 FTIM1_NOR_TRAD_NOR(0xb) | \
49 FTIM1_NOR_TSEQRAD_NOR(0x9))
50#define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x1) | \
51 FTIM2_NOR_TCH(0x4) | \
52 FTIM2_NOR_TWPH(0x8) | \
53 FTIM2_NOR_TWP(0x10))
54#define CONFIG_SYS_NOR_FTIM3 0
55#define CONFIG_SYS_IFC_CCR 0x01000000
56
Mingkai Hueee86ff2015-10-26 19:47:52 +080057#define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */
58#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
59#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
60
61#define CONFIG_SYS_FLASH_EMPTY_INFO
62#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE_PHYS }
63
Mingkai Hueee86ff2015-10-26 19:47:52 +080064#define CONFIG_SYS_WRITE_SWAPPED_DATA
65
66/*
67 * NAND Flash Definitions
68 */
Mingkai Hueee86ff2015-10-26 19:47:52 +080069
70#define CONFIG_SYS_NAND_BASE 0x7e800000
71#define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE
72
73#define CONFIG_SYS_NAND_CSPR_EXT (0x0)
74#define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
75 | CSPR_PORT_SIZE_8 \
76 | CSPR_MSEL_NAND \
77 | CSPR_V)
78#define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024)
79#define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
80 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
81 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \
82 | CSOR_NAND_RAL_3 /* RAL = 3 Bytes */ \
83 | CSOR_NAND_PGS_2K /* Page Size = 2K */ \
84 | CSOR_NAND_SPRZ_64 /* Spare size = 64 */ \
85 | CSOR_NAND_PB(64)) /* 64 Pages Per Block */
86
Mingkai Hueee86ff2015-10-26 19:47:52 +080087#define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x7) | \
88 FTIM0_NAND_TWP(0x18) | \
89 FTIM0_NAND_TWCHT(0x7) | \
90 FTIM0_NAND_TWH(0xa))
91#define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \
92 FTIM1_NAND_TWBE(0x39) | \
93 FTIM1_NAND_TRR(0xe) | \
94 FTIM1_NAND_TRP(0x18))
95#define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0xf) | \
96 FTIM2_NAND_TREH(0xa) | \
97 FTIM2_NAND_TWHRE(0x1e))
98#define CONFIG_SYS_NAND_FTIM3 0x0
99
100#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
101#define CONFIG_SYS_MAX_NAND_DEVICE 1
102#define CONFIG_MTD_NAND_VERIFY_WRITE
Mingkai Hueee86ff2015-10-26 19:47:52 +0800103
Gong Qianyu8168a0f2015-10-26 19:47:53 +0800104#ifdef CONFIG_NAND_BOOT
105#define CONFIG_SPL_PAD_TO 0x20000 /* block aligned */
Ruchika Guptaba688752017-04-17 18:07:18 +0530106#define CONFIG_SYS_NAND_U_BOOT_SIZE (1024 << 10)
Gong Qianyu8168a0f2015-10-26 19:47:53 +0800107#endif
108
Mingkai Hueee86ff2015-10-26 19:47:52 +0800109/*
110 * CPLD
111 */
112#define CONFIG_SYS_CPLD_BASE 0x7fb00000
113#define CPLD_BASE_PHYS CONFIG_SYS_CPLD_BASE
114
115#define CONFIG_SYS_CPLD_CSPR_EXT (0x0)
116#define CONFIG_SYS_CPLD_CSPR (CSPR_PHYS_ADDR(CPLD_BASE_PHYS) | \
117 CSPR_PORT_SIZE_8 | \
118 CSPR_MSEL_GPCM | \
119 CSPR_V)
120#define CONFIG_SYS_CPLD_AMASK IFC_AMASK(64 * 1024)
121#define CONFIG_SYS_CPLD_CSOR (CSOR_NOR_ADM_SHIFT(4) | \
122 CSOR_NOR_NOR_MODE_AVD_NOR | \
123 CSOR_NOR_TRHZ_80)
124
125/* CPLD Timing parameters for IFC GPCM */
126#define CONFIG_SYS_CPLD_FTIM0 (FTIM0_GPCM_TACSE(0xf) | \
127 FTIM0_GPCM_TEADC(0xf) | \
128 FTIM0_GPCM_TEAHC(0xf))
129#define CONFIG_SYS_CPLD_FTIM1 (FTIM1_GPCM_TACO(0xff) | \
130 FTIM1_GPCM_TRAD(0x3f))
131#define CONFIG_SYS_CPLD_FTIM2 (FTIM2_GPCM_TCS(0xf) | \
132 FTIM2_GPCM_TCH(0xf) | \
133 FTIM2_GPCM_TWP(0xff))
134#define CONFIG_SYS_CPLD_FTIM3 0x0
135
136/* IFC Timing Params */
Rajesh Bhagatb89aed42018-11-05 18:02:44 +0000137#ifdef CONFIG_TFABOOT
138#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR_CSPR_EXT
139#define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR_CSPR
140#define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK
141#define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR
142#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0
143#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1
144#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2
145#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3
146
147#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NAND_CSPR_EXT
148#define CONFIG_SYS_CSPR1 CONFIG_SYS_NAND_CSPR
149#define CONFIG_SYS_AMASK1 CONFIG_SYS_NAND_AMASK
150#define CONFIG_SYS_CSOR1 CONFIG_SYS_NAND_CSOR
151#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NAND_FTIM0
152#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NAND_FTIM1
153#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NAND_FTIM2
154#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NAND_FTIM3
155#else
Gong Qianyu8168a0f2015-10-26 19:47:53 +0800156#ifdef CONFIG_NAND_BOOT
157#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT
158#define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR
159#define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK
160#define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR
161#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0
162#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1
163#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2
164#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3
165
166#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR_CSPR_EXT
167#define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR_CSPR
168#define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK
169#define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR
170#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0
171#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1
172#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2
173#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3
174#else
Mingkai Hueee86ff2015-10-26 19:47:52 +0800175#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR_CSPR_EXT
176#define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR_CSPR
177#define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK
178#define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR
179#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0
180#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1
181#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2
182#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3
183
184#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NAND_CSPR_EXT
185#define CONFIG_SYS_CSPR1 CONFIG_SYS_NAND_CSPR
186#define CONFIG_SYS_AMASK1 CONFIG_SYS_NAND_AMASK
187#define CONFIG_SYS_CSOR1 CONFIG_SYS_NAND_CSOR
188#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NAND_FTIM0
189#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NAND_FTIM1
190#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NAND_FTIM2
191#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NAND_FTIM3
Gong Qianyu8168a0f2015-10-26 19:47:53 +0800192#endif
Rajesh Bhagatb89aed42018-11-05 18:02:44 +0000193#endif
Mingkai Hueee86ff2015-10-26 19:47:52 +0800194
195#define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_CPLD_CSPR_EXT
196#define CONFIG_SYS_CSPR2 CONFIG_SYS_CPLD_CSPR
197#define CONFIG_SYS_AMASK2 CONFIG_SYS_CPLD_AMASK
198#define CONFIG_SYS_CSOR2 CONFIG_SYS_CPLD_CSOR
199#define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_CPLD_FTIM0
200#define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_CPLD_FTIM1
201#define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_CPLD_FTIM2
202#define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_CPLD_FTIM3
203
204/* EEPROM */
Sumit Garg2a2857b2017-03-30 09:52:38 +0530205#ifndef SPL_NO_EEPROM
Mingkai Hueee86ff2015-10-26 19:47:52 +0800206#define CONFIG_SYS_I2C_EEPROM_NXID
207#define CONFIG_SYS_EEPROM_BUS_NUM 0
Sumit Garg2a2857b2017-03-30 09:52:38 +0530208#endif
Mingkai Hueee86ff2015-10-26 19:47:52 +0800209
210/*
211 * Environment
212 */
Gong Qianyu8168a0f2015-10-26 19:47:53 +0800213
Shaohui Xie04643262015-10-26 19:47:54 +0800214/* FMan */
Sumit Garg2a2857b2017-03-30 09:52:38 +0530215#ifndef SPL_NO_FMAN
York Sun5f0580c2017-04-25 08:39:52 -0700216#define AQR105_IRQ_MASK 0x40000000
217
York Sun5f0580c2017-04-25 08:39:52 -0700218#ifdef CONFIG_SYS_DPAA_FMAN
Shaohui Xie04643262015-10-26 19:47:54 +0800219#define RGMII_PHY1_ADDR 0x1
220#define RGMII_PHY2_ADDR 0x2
221
222#define QSGMII_PORT1_PHY_ADDR 0x4
223#define QSGMII_PORT2_PHY_ADDR 0x5
224#define QSGMII_PORT3_PHY_ADDR 0x6
225#define QSGMII_PORT4_PHY_ADDR 0x7
226
227#define FM1_10GEC1_PHY_ADDR 0x1
228
229#define CONFIG_ETHPRIME "FM1@DTSEC3"
230#endif
Sumit Garg2a2857b2017-03-30 09:52:38 +0530231#endif
Shaohui Xie04643262015-10-26 19:47:54 +0800232
Po Liu2271aa12016-05-18 10:09:38 +0800233/* SATA */
Sumit Garg2a2857b2017-03-30 09:52:38 +0530234#ifndef SPL_NO_SATA
Po Liu2271aa12016-05-18 10:09:38 +0800235#define SCSI_VEND_ID 0x1b4b
236#define SCSI_DEV_ID 0x9170
237#define CONFIG_SCSI_DEV_LIST {SCSI_VEND_ID, SCSI_DEV_ID}
Sumit Garg2a2857b2017-03-30 09:52:38 +0530238#endif
Po Liu2271aa12016-05-18 10:09:38 +0800239
Aneesh Bansalb3e98202015-12-08 13:54:29 +0530240#include <asm/fsl_secure_boot.h>
241
Mingkai Hueee86ff2015-10-26 19:47:52 +0800242#endif /* __LS1043ARDB_H__ */