Tom Rini | 10e4779 | 2018-05-06 17:58:06 -0400 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0+ */ |
Chunhe Lan | 8e4f3ff | 2014-04-14 18:42:06 +0800 | [diff] [blame] | 2 | /* |
| 3 | * Copyright 2014 Freescale Semiconductor, Inc. |
Yangbo Lu | bb32e68 | 2021-06-03 10:51:19 +0800 | [diff] [blame] | 4 | * Copyright 2020-2021 NXP |
Chunhe Lan | 8e4f3ff | 2014-04-14 18:42:06 +0800 | [diff] [blame] | 5 | */ |
| 6 | |
| 7 | /* |
| 8 | * T4240 RDB board configuration file |
| 9 | */ |
| 10 | #ifndef __CONFIG_H |
| 11 | #define __CONFIG_H |
| 12 | |
Simon Glass | fb64e36 | 2020-05-10 11:40:09 -0600 | [diff] [blame] | 13 | #include <linux/stringify.h> |
| 14 | |
Chunhe Lan | 8e4f3ff | 2014-04-14 18:42:06 +0800 | [diff] [blame] | 15 | #define CONFIG_FSL_SATA_V2 |
| 16 | #define CONFIG_PCIE4 |
| 17 | |
| 18 | #define CONFIG_ICS307_REFCLK_HZ 25000000 /* ICS307 ref clk freq */ |
| 19 | |
| 20 | #ifdef CONFIG_RAMBOOT_PBL |
Chunhe Lan | 66cba6b | 2015-03-20 17:08:54 +0800 | [diff] [blame] | 21 | #ifndef CONFIG_SDCARD |
| 22 | #define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE |
| 23 | #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc |
| 24 | #else |
Chunhe Lan | 66cba6b | 2015-03-20 17:08:54 +0800 | [diff] [blame] | 25 | #define CONFIG_SPL_FLUSH_IMAGE |
Chunhe Lan | 66cba6b | 2015-03-20 17:08:54 +0800 | [diff] [blame] | 26 | #define CONFIG_SPL_PAD_TO 0x40000 |
| 27 | #define CONFIG_SPL_MAX_SIZE 0x28000 |
| 28 | #define RESET_VECTOR_OFFSET 0x27FFC |
| 29 | #define BOOT_PAGE_OFFSET 0x27000 |
| 30 | |
| 31 | #ifdef CONFIG_SDCARD |
| 32 | #define CONFIG_RESET_VECTOR_ADDRESS 0x200FFC |
Chunhe Lan | 66cba6b | 2015-03-20 17:08:54 +0800 | [diff] [blame] | 33 | #define CONFIG_SYS_MMC_U_BOOT_SIZE (768 << 10) |
| 34 | #define CONFIG_SYS_MMC_U_BOOT_DST 0x00200000 |
| 35 | #define CONFIG_SYS_MMC_U_BOOT_START 0x00200000 |
| 36 | #define CONFIG_SYS_MMC_U_BOOT_OFFS (260 << 10) |
| 37 | #ifndef CONFIG_SPL_BUILD |
| 38 | #define CONFIG_SYS_MPC85XX_NO_RESETVEC |
| 39 | #endif |
Chunhe Lan | 66cba6b | 2015-03-20 17:08:54 +0800 | [diff] [blame] | 40 | #endif |
| 41 | |
| 42 | #ifdef CONFIG_SPL_BUILD |
| 43 | #define CONFIG_SPL_SKIP_RELOCATE |
| 44 | #define CONFIG_SPL_COMMON_INIT_DDR |
| 45 | #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE |
Chunhe Lan | 8e4f3ff | 2014-04-14 18:42:06 +0800 | [diff] [blame] | 46 | #endif |
| 47 | |
Chunhe Lan | 66cba6b | 2015-03-20 17:08:54 +0800 | [diff] [blame] | 48 | #endif |
| 49 | #endif /* CONFIG_RAMBOOT_PBL */ |
| 50 | |
Chunhe Lan | 8e4f3ff | 2014-04-14 18:42:06 +0800 | [diff] [blame] | 51 | /* High Level Configuration Options */ |
Chunhe Lan | 8e4f3ff | 2014-04-14 18:42:06 +0800 | [diff] [blame] | 52 | #define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */ |
Chunhe Lan | 8e4f3ff | 2014-04-14 18:42:06 +0800 | [diff] [blame] | 53 | |
Chunhe Lan | 8e4f3ff | 2014-04-14 18:42:06 +0800 | [diff] [blame] | 54 | #ifndef CONFIG_RESET_VECTOR_ADDRESS |
| 55 | #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc |
| 56 | #endif |
| 57 | |
| 58 | #define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */ |
York Sun | fe84507 | 2016-12-28 08:43:45 -0800 | [diff] [blame] | 59 | #define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS |
Robert P. J. Day | a809981 | 2016-05-03 19:52:49 -0400 | [diff] [blame] | 60 | #define CONFIG_PCIE1 /* PCIE controller 1 */ |
| 61 | #define CONFIG_PCIE2 /* PCIE controller 2 */ |
| 62 | #define CONFIG_PCIE3 /* PCIE controller 3 */ |
Chunhe Lan | 8e4f3ff | 2014-04-14 18:42:06 +0800 | [diff] [blame] | 63 | |
Chunhe Lan | 8e4f3ff | 2014-04-14 18:42:06 +0800 | [diff] [blame] | 64 | /* |
| 65 | * These can be toggled for performance analysis, otherwise use default. |
| 66 | */ |
| 67 | #define CONFIG_SYS_CACHE_STASHING |
Chunhe Lan | 8e4f3ff | 2014-04-14 18:42:06 +0800 | [diff] [blame] | 68 | #ifdef CONFIG_DDR_ECC |
Chunhe Lan | 8e4f3ff | 2014-04-14 18:42:06 +0800 | [diff] [blame] | 69 | #define CONFIG_MEM_INIT_VALUE 0xdeadbeef |
| 70 | #endif |
| 71 | |
| 72 | #define CONFIG_ENABLE_36BIT_PHYS |
| 73 | |
Chunhe Lan | 8e4f3ff | 2014-04-14 18:42:06 +0800 | [diff] [blame] | 74 | /* |
| 75 | * Config the L3 Cache as L3 SRAM |
| 76 | */ |
Chunhe Lan | 66cba6b | 2015-03-20 17:08:54 +0800 | [diff] [blame] | 77 | #define CONFIG_SYS_INIT_L3_ADDR 0xFFFC0000 |
| 78 | #define CONFIG_SYS_L3_SIZE (512 << 10) |
| 79 | #define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L3_ADDR + 32 * 1024) |
Tom Rini | 5cd7ece | 2019-11-18 20:02:10 -0500 | [diff] [blame] | 80 | #define SPL_ENV_ADDR (CONFIG_SPL_GD_ADDR + 4 * 1024) |
Chunhe Lan | 66cba6b | 2015-03-20 17:08:54 +0800 | [diff] [blame] | 81 | #define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SPL_GD_ADDR + 12 * 1024) |
| 82 | #define CONFIG_SPL_RELOC_MALLOC_SIZE (50 << 10) |
| 83 | #define CONFIG_SPL_RELOC_STACK (CONFIG_SPL_GD_ADDR + 64 * 1024) |
Chunhe Lan | 8e4f3ff | 2014-04-14 18:42:06 +0800 | [diff] [blame] | 84 | |
| 85 | #define CONFIG_SYS_DCSRBAR 0xf0000000 |
| 86 | #define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull |
| 87 | |
| 88 | /* |
| 89 | * DDR Setup |
| 90 | */ |
| 91 | #define CONFIG_VERY_BIG_RAM |
| 92 | #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 |
| 93 | #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE |
| 94 | |
Chunhe Lan | 8e4f3ff | 2014-04-14 18:42:06 +0800 | [diff] [blame] | 95 | #define CONFIG_DIMM_SLOTS_PER_CTLR 1 |
Chunhe Lan | 8e4f3ff | 2014-04-14 18:42:06 +0800 | [diff] [blame] | 96 | |
Chunhe Lan | 8e4f3ff | 2014-04-14 18:42:06 +0800 | [diff] [blame] | 97 | /* |
| 98 | * IFC Definitions |
| 99 | */ |
| 100 | #define CONFIG_SYS_FLASH_BASE 0xe0000000 |
| 101 | #define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE) |
| 102 | |
Chunhe Lan | 66cba6b | 2015-03-20 17:08:54 +0800 | [diff] [blame] | 103 | #ifdef CONFIG_SPL_BUILD |
| 104 | #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE |
| 105 | #else |
Chunhe Lan | 8e4f3ff | 2014-04-14 18:42:06 +0800 | [diff] [blame] | 106 | #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE |
Chunhe Lan | 66cba6b | 2015-03-20 17:08:54 +0800 | [diff] [blame] | 107 | #endif |
Chunhe Lan | 8e4f3ff | 2014-04-14 18:42:06 +0800 | [diff] [blame] | 108 | |
Chunhe Lan | 8e4f3ff | 2014-04-14 18:42:06 +0800 | [diff] [blame] | 109 | #define CONFIG_HWCONFIG |
| 110 | |
| 111 | /* define to use L1 as initial stack */ |
| 112 | #define CONFIG_L1_INIT_RAM |
| 113 | #define CONFIG_SYS_INIT_RAM_LOCK |
| 114 | #define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */ |
| 115 | #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf |
York Sun | ee7b483 | 2015-08-17 13:31:51 -0700 | [diff] [blame] | 116 | #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe03c000 |
Chunhe Lan | 8e4f3ff | 2014-04-14 18:42:06 +0800 | [diff] [blame] | 117 | /* The assembler doesn't like typecast */ |
| 118 | #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \ |
| 119 | ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \ |
| 120 | CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW) |
| 121 | #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 |
| 122 | |
| 123 | #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ |
| 124 | GENERATED_GBL_DATA_SIZE) |
| 125 | #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET |
| 126 | |
Chunhe Lan | 66cba6b | 2015-03-20 17:08:54 +0800 | [diff] [blame] | 127 | #define CONFIG_SYS_MONITOR_LEN (768 * 1024) |
Chunhe Lan | 8e4f3ff | 2014-04-14 18:42:06 +0800 | [diff] [blame] | 128 | |
| 129 | /* Serial Port - controlled on board with jumper J8 |
| 130 | * open - index 2 |
| 131 | * shorted - index 1 |
| 132 | */ |
Chunhe Lan | 8e4f3ff | 2014-04-14 18:42:06 +0800 | [diff] [blame] | 133 | #define CONFIG_SYS_NS16550_SERIAL |
| 134 | #define CONFIG_SYS_NS16550_REG_SIZE 1 |
| 135 | #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2) |
| 136 | |
| 137 | #define CONFIG_SYS_BAUDRATE_TABLE \ |
| 138 | {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} |
| 139 | |
| 140 | #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500) |
| 141 | #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600) |
| 142 | #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500) |
| 143 | #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600) |
| 144 | |
Chunhe Lan | 8e4f3ff | 2014-04-14 18:42:06 +0800 | [diff] [blame] | 145 | /* I2C */ |
Biwen Li | 3e9d395 | 2020-05-01 20:04:17 +0800 | [diff] [blame] | 146 | |
Chunhe Lan | 8e4f3ff | 2014-04-14 18:42:06 +0800 | [diff] [blame] | 147 | /* |
| 148 | * General PCI |
| 149 | * Memory space is mapped 1-1, but I/O space must start from 0. |
| 150 | */ |
| 151 | |
| 152 | /* controller 1, direct to uli, tgtid 3, Base address 20000 */ |
| 153 | #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 |
Chunhe Lan | 8e4f3ff | 2014-04-14 18:42:06 +0800 | [diff] [blame] | 154 | #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull |
Chunhe Lan | 8e4f3ff | 2014-04-14 18:42:06 +0800 | [diff] [blame] | 155 | #define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000 |
Chunhe Lan | 8e4f3ff | 2014-04-14 18:42:06 +0800 | [diff] [blame] | 156 | #define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull |
Chunhe Lan | 8e4f3ff | 2014-04-14 18:42:06 +0800 | [diff] [blame] | 157 | |
| 158 | /* controller 2, Slot 2, tgtid 2, Base address 201000 */ |
| 159 | #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000 |
Chunhe Lan | 8e4f3ff | 2014-04-14 18:42:06 +0800 | [diff] [blame] | 160 | #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull |
Chunhe Lan | 8e4f3ff | 2014-04-14 18:42:06 +0800 | [diff] [blame] | 161 | #define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000 |
Chunhe Lan | 8e4f3ff | 2014-04-14 18:42:06 +0800 | [diff] [blame] | 162 | #define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull |
Chunhe Lan | 8e4f3ff | 2014-04-14 18:42:06 +0800 | [diff] [blame] | 163 | |
| 164 | /* controller 3, Slot 1, tgtid 1, Base address 202000 */ |
| 165 | #define CONFIG_SYS_PCIE3_MEM_VIRT 0xc0000000 |
Chunhe Lan | 8e4f3ff | 2014-04-14 18:42:06 +0800 | [diff] [blame] | 166 | #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc40000000ull |
Chunhe Lan | 8e4f3ff | 2014-04-14 18:42:06 +0800 | [diff] [blame] | 167 | #define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000 |
Chunhe Lan | 8e4f3ff | 2014-04-14 18:42:06 +0800 | [diff] [blame] | 168 | #define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull |
Chunhe Lan | 8e4f3ff | 2014-04-14 18:42:06 +0800 | [diff] [blame] | 169 | |
| 170 | /* controller 4, Base address 203000 */ |
| 171 | #define CONFIG_SYS_PCIE4_MEM_BUS 0xe0000000 |
| 172 | #define CONFIG_SYS_PCIE4_MEM_PHYS 0xc60000000ull |
Chunhe Lan | 8e4f3ff | 2014-04-14 18:42:06 +0800 | [diff] [blame] | 173 | #define CONFIG_SYS_PCIE4_IO_PHYS 0xff8030000ull |
Chunhe Lan | 8e4f3ff | 2014-04-14 18:42:06 +0800 | [diff] [blame] | 174 | |
| 175 | #ifdef CONFIG_PCI |
Chunhe Lan | 8e4f3ff | 2014-04-14 18:42:06 +0800 | [diff] [blame] | 176 | #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ |
Chunhe Lan | 8e4f3ff | 2014-04-14 18:42:06 +0800 | [diff] [blame] | 177 | #endif /* CONFIG_PCI */ |
| 178 | |
| 179 | /* SATA */ |
| 180 | #ifdef CONFIG_FSL_SATA_V2 |
Chunhe Lan | 8e4f3ff | 2014-04-14 18:42:06 +0800 | [diff] [blame] | 181 | #define CONFIG_SATA1 |
| 182 | #define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR |
| 183 | #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA |
| 184 | #define CONFIG_SATA2 |
| 185 | #define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR |
| 186 | #define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA |
| 187 | |
| 188 | #define CONFIG_LBA48 |
Chunhe Lan | 8e4f3ff | 2014-04-14 18:42:06 +0800 | [diff] [blame] | 189 | #endif |
| 190 | |
| 191 | #ifdef CONFIG_FMAN_ENET |
Chunhe Lan | 8e4f3ff | 2014-04-14 18:42:06 +0800 | [diff] [blame] | 192 | #define CONFIG_ETHPRIME "FM1@DTSEC1" |
Chunhe Lan | 8e4f3ff | 2014-04-14 18:42:06 +0800 | [diff] [blame] | 193 | #endif |
| 194 | |
| 195 | /* |
| 196 | * Environment |
| 197 | */ |
| 198 | #define CONFIG_LOADS_ECHO /* echo on for serial download */ |
| 199 | #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */ |
| 200 | |
| 201 | /* |
Chunhe Lan | 8e4f3ff | 2014-04-14 18:42:06 +0800 | [diff] [blame] | 202 | * Miscellaneous configurable options |
| 203 | */ |
Chunhe Lan | 8e4f3ff | 2014-04-14 18:42:06 +0800 | [diff] [blame] | 204 | |
| 205 | /* |
| 206 | * For booting Linux, the board info and command line data |
| 207 | * have to be in the first 64 MB of memory, since this is |
| 208 | * the maximum mapped by the Linux kernel during initialization. |
| 209 | */ |
| 210 | #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/ |
| 211 | #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ |
| 212 | |
Chunhe Lan | 8e4f3ff | 2014-04-14 18:42:06 +0800 | [diff] [blame] | 213 | /* |
| 214 | * Environment Configuration |
| 215 | */ |
| 216 | #define CONFIG_ROOTPATH "/opt/nfsroot" |
Chunhe Lan | 8e4f3ff | 2014-04-14 18:42:06 +0800 | [diff] [blame] | 217 | #define CONFIG_UBOOTPATH "u-boot.bin" /* U-Boot image on TFTP server*/ |
| 218 | |
Tom Rini | 9aed2af | 2021-08-19 14:29:00 -0400 | [diff] [blame] | 219 | #define HVBOOT \ |
Chunhe Lan | 8e4f3ff | 2014-04-14 18:42:06 +0800 | [diff] [blame] | 220 | "setenv bootargs config-addr=0x60000000; " \ |
| 221 | "bootm 0x01000000 - 0x00f00000" |
| 222 | |
Chunhe Lan | 8e4f3ff | 2014-04-14 18:42:06 +0800 | [diff] [blame] | 223 | /* |
| 224 | * DDR Setup |
| 225 | */ |
| 226 | #define CONFIG_SYS_SPD_BUS_NUM 0 |
| 227 | #define SPD_EEPROM_ADDRESS1 0x52 |
| 228 | #define SPD_EEPROM_ADDRESS2 0x54 |
| 229 | #define SPD_EEPROM_ADDRESS3 0x56 |
| 230 | #define SPD_EEPROM_ADDRESS SPD_EEPROM_ADDRESS1 /* for p3041/p5010 */ |
| 231 | #define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */ |
| 232 | |
| 233 | /* |
| 234 | * IFC Definitions |
| 235 | */ |
| 236 | #define CONFIG_SYS_NOR0_CSPR_EXT (0xf) |
| 237 | #define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \ |
| 238 | + 0x8000000) | \ |
| 239 | CSPR_PORT_SIZE_16 | \ |
| 240 | CSPR_MSEL_NOR | \ |
| 241 | CSPR_V) |
| 242 | #define CONFIG_SYS_NOR1_CSPR_EXT (0xf) |
| 243 | #define CONFIG_SYS_NOR1_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \ |
| 244 | CSPR_PORT_SIZE_16 | \ |
| 245 | CSPR_MSEL_NOR | \ |
| 246 | CSPR_V) |
| 247 | #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024) |
| 248 | /* NOR Flash Timing Params */ |
| 249 | #define CONFIG_SYS_NOR_CSOR CSOR_NAND_TRHZ_80 |
| 250 | |
| 251 | #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \ |
| 252 | FTIM0_NOR_TEADC(0x5) | \ |
| 253 | FTIM0_NOR_TEAHC(0x5)) |
| 254 | #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \ |
| 255 | FTIM1_NOR_TRAD_NOR(0x1A) |\ |
| 256 | FTIM1_NOR_TSEQRAD_NOR(0x13)) |
| 257 | #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \ |
| 258 | FTIM2_NOR_TCH(0x4) | \ |
| 259 | FTIM2_NOR_TWPH(0x0E) | \ |
| 260 | FTIM2_NOR_TWP(0x1c)) |
| 261 | #define CONFIG_SYS_NOR_FTIM3 0x0 |
| 262 | |
| 263 | #define CONFIG_SYS_FLASH_QUIET_TEST |
| 264 | #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ |
| 265 | |
Chunhe Lan | 8e4f3ff | 2014-04-14 18:42:06 +0800 | [diff] [blame] | 266 | #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ |
| 267 | #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ |
| 268 | #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ |
| 269 | |
| 270 | #define CONFIG_SYS_FLASH_EMPTY_INFO |
| 271 | #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS \ |
| 272 | + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS} |
| 273 | |
| 274 | /* NAND Flash on IFC */ |
Chunhe Lan | 8e4f3ff | 2014-04-14 18:42:06 +0800 | [diff] [blame] | 275 | #define CONFIG_SYS_NAND_MAX_ECCPOS 256 |
| 276 | #define CONFIG_SYS_NAND_MAX_OOBFREE 2 |
| 277 | #define CONFIG_SYS_NAND_BASE 0xff800000 |
| 278 | #define CONFIG_SYS_NAND_BASE_PHYS (0xf00000000ull | CONFIG_SYS_NAND_BASE) |
| 279 | |
| 280 | #define CONFIG_SYS_NAND_CSPR_EXT (0xf) |
| 281 | #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ |
| 282 | | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \ |
| 283 | | CSPR_MSEL_NAND /* MSEL = NAND */ \ |
| 284 | | CSPR_V) |
| 285 | #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024) |
| 286 | |
| 287 | #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ |
| 288 | | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ |
| 289 | | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ |
| 290 | | CSOR_NAND_RAL_3 /* RAL = 2Byes */ \ |
| 291 | | CSOR_NAND_PGS_4K /* Page Size = 4K */ \ |
| 292 | | CSOR_NAND_SPRZ_224 /* Spare size = 224 */ \ |
| 293 | | CSOR_NAND_PB(128)) /*Page Per Block = 128*/ |
| 294 | |
Chunhe Lan | 8e4f3ff | 2014-04-14 18:42:06 +0800 | [diff] [blame] | 295 | /* ONFI NAND Flash mode0 Timing Params */ |
| 296 | #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \ |
| 297 | FTIM0_NAND_TWP(0x18) | \ |
| 298 | FTIM0_NAND_TWCHT(0x07) | \ |
| 299 | FTIM0_NAND_TWH(0x0a)) |
| 300 | #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \ |
| 301 | FTIM1_NAND_TWBE(0x39) | \ |
| 302 | FTIM1_NAND_TRR(0x0e) | \ |
| 303 | FTIM1_NAND_TRP(0x18)) |
| 304 | #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \ |
| 305 | FTIM2_NAND_TREH(0x0a) | \ |
| 306 | FTIM2_NAND_TWHRE(0x1e)) |
| 307 | #define CONFIG_SYS_NAND_FTIM3 0x0 |
| 308 | |
| 309 | #define CONFIG_SYS_NAND_DDR_LAW 11 |
| 310 | #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } |
| 311 | #define CONFIG_SYS_MAX_NAND_DEVICE 1 |
Chunhe Lan | 8e4f3ff | 2014-04-14 18:42:06 +0800 | [diff] [blame] | 312 | |
Miquel Raynal | d093536 | 2019-10-03 19:50:03 +0200 | [diff] [blame] | 313 | #if defined(CONFIG_MTD_RAW_NAND) |
Chunhe Lan | 8e4f3ff | 2014-04-14 18:42:06 +0800 | [diff] [blame] | 314 | #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT |
| 315 | #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR |
| 316 | #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK |
| 317 | #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR |
| 318 | #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0 |
| 319 | #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1 |
| 320 | #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2 |
| 321 | #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3 |
| 322 | #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR0_CSPR_EXT |
| 323 | #define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR0_CSPR |
| 324 | #define CONFIG_SYS_AMASK2 CONFIG_SYS_NOR_AMASK |
| 325 | #define CONFIG_SYS_CSOR2 CONFIG_SYS_NOR_CSOR |
| 326 | #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NOR_FTIM0 |
| 327 | #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NOR_FTIM1 |
| 328 | #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NOR_FTIM2 |
| 329 | #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NOR_FTIM3 |
| 330 | #else |
| 331 | #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT |
| 332 | #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR |
| 333 | #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK |
| 334 | #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR |
| 335 | #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 |
| 336 | #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 |
| 337 | #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 |
| 338 | #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 |
| 339 | #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NAND_CSPR_EXT |
| 340 | #define CONFIG_SYS_CSPR1 CONFIG_SYS_NAND_CSPR |
| 341 | #define CONFIG_SYS_AMASK1 CONFIG_SYS_NAND_AMASK |
| 342 | #define CONFIG_SYS_CSOR1 CONFIG_SYS_NAND_CSOR |
| 343 | #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NAND_FTIM0 |
| 344 | #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NAND_FTIM1 |
| 345 | #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NAND_FTIM2 |
| 346 | #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NAND_FTIM3 |
| 347 | #endif |
| 348 | #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR1_CSPR_EXT |
| 349 | #define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR1_CSPR |
| 350 | #define CONFIG_SYS_AMASK2 CONFIG_SYS_NOR_AMASK |
| 351 | #define CONFIG_SYS_CSOR2 CONFIG_SYS_NOR_CSOR |
| 352 | #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NOR_FTIM0 |
| 353 | #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NOR_FTIM1 |
| 354 | #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NOR_FTIM2 |
| 355 | #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NOR_FTIM3 |
| 356 | |
Chunhe Lan | c3eb88d | 2014-09-12 14:47:09 +0800 | [diff] [blame] | 357 | /* CPLD on IFC */ |
| 358 | #define CONFIG_SYS_CPLD_BASE 0xffdf0000 |
| 359 | #define CONFIG_SYS_CPLD_BASE_PHYS (0xf00000000ull | CONFIG_SYS_CPLD_BASE) |
| 360 | #define CONFIG_SYS_CSPR3_EXT (0xf) |
| 361 | #define CONFIG_SYS_CSPR3 (CSPR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE_PHYS) \ |
| 362 | | CSPR_PORT_SIZE_8 \ |
| 363 | | CSPR_MSEL_GPCM \ |
| 364 | | CSPR_V) |
| 365 | |
Rajesh Bhagat | 28663d8 | 2018-11-05 18:01:19 +0000 | [diff] [blame] | 366 | #define CONFIG_SYS_AMASK3 IFC_AMASK(64 * 1024) |
Chunhe Lan | c3eb88d | 2014-09-12 14:47:09 +0800 | [diff] [blame] | 367 | #define CONFIG_SYS_CSOR3 0x0 |
| 368 | |
| 369 | /* CPLD Timing parameters for IFC CS3 */ |
| 370 | #define CONFIG_SYS_CS3_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \ |
| 371 | FTIM0_GPCM_TEADC(0x0e) | \ |
| 372 | FTIM0_GPCM_TEAHC(0x0e)) |
| 373 | #define CONFIG_SYS_CS3_FTIM1 (FTIM1_GPCM_TACO(0x0e) | \ |
| 374 | FTIM1_GPCM_TRAD(0x1f)) |
| 375 | #define CONFIG_SYS_CS3_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \ |
Chunhe Lan | 6e2ee5b | 2014-10-20 16:03:15 +0800 | [diff] [blame] | 376 | FTIM2_GPCM_TCH(0x8) | \ |
Chunhe Lan | c3eb88d | 2014-09-12 14:47:09 +0800 | [diff] [blame] | 377 | FTIM2_GPCM_TWP(0x1f)) |
| 378 | #define CONFIG_SYS_CS3_FTIM3 0x0 |
| 379 | |
Chunhe Lan | 8e4f3ff | 2014-04-14 18:42:06 +0800 | [diff] [blame] | 380 | #if defined(CONFIG_RAMBOOT_PBL) |
| 381 | #define CONFIG_SYS_RAMBOOT |
| 382 | #endif |
| 383 | |
Chunhe Lan | 8e4f3ff | 2014-04-14 18:42:06 +0800 | [diff] [blame] | 384 | /* I2C */ |
Chunhe Lan | 8e4f3ff | 2014-04-14 18:42:06 +0800 | [diff] [blame] | 385 | #define I2C_MUX_PCA_ADDR_PRI 0x77 /* I2C bus multiplexer,primary */ |
| 386 | #define I2C_MUX_PCA_ADDR_SEC 0x76 /* I2C bus multiplexer,secondary */ |
| 387 | |
| 388 | #define I2C_MUX_CH_DEFAULT 0x8 |
| 389 | #define I2C_MUX_CH_VOL_MONITOR 0xa |
| 390 | #define I2C_MUX_CH_VSC3316_FS 0xc |
| 391 | #define I2C_MUX_CH_VSC3316_BS 0xd |
| 392 | |
| 393 | /* Voltage monitor on channel 2*/ |
| 394 | #define I2C_VOL_MONITOR_ADDR 0x40 |
| 395 | #define I2C_VOL_MONITOR_BUS_V_OFFSET 0x2 |
| 396 | #define I2C_VOL_MONITOR_BUS_V_OVF 0x1 |
| 397 | #define I2C_VOL_MONITOR_BUS_V_SHIFT 3 |
| 398 | |
Ying Zhang | ff77905 | 2016-01-22 12:15:13 +0800 | [diff] [blame] | 399 | /* The lowest and highest voltage allowed for T4240RDB */ |
| 400 | #define VDD_MV_MIN 819 |
| 401 | #define VDD_MV_MAX 1212 |
| 402 | |
Chunhe Lan | 8e4f3ff | 2014-04-14 18:42:06 +0800 | [diff] [blame] | 403 | /* |
| 404 | * eSPI - Enhanced SPI |
| 405 | */ |
Chunhe Lan | 8e4f3ff | 2014-04-14 18:42:06 +0800 | [diff] [blame] | 406 | |
Chunhe Lan | 8e4f3ff | 2014-04-14 18:42:06 +0800 | [diff] [blame] | 407 | /* Qman/Bman */ |
| 408 | #ifndef CONFIG_NOBQFMAN |
Chunhe Lan | 8e4f3ff | 2014-04-14 18:42:06 +0800 | [diff] [blame] | 409 | #define CONFIG_SYS_BMAN_NUM_PORTALS 50 |
| 410 | #define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000 |
| 411 | #define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull |
| 412 | #define CONFIG_SYS_BMAN_MEM_SIZE 0x02000000 |
Jeffrey Ladouceur | ff2c646 | 2014-12-08 14:54:01 -0500 | [diff] [blame] | 413 | #define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000 |
| 414 | #define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000 |
| 415 | #define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE |
| 416 | #define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) |
| 417 | #define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \ |
| 418 | CONFIG_SYS_BMAN_CENA_SIZE) |
| 419 | #define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) |
| 420 | #define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08 |
Chunhe Lan | 8e4f3ff | 2014-04-14 18:42:06 +0800 | [diff] [blame] | 421 | #define CONFIG_SYS_QMAN_NUM_PORTALS 50 |
| 422 | #define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000 |
| 423 | #define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull |
| 424 | #define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000 |
Jeffrey Ladouceur | ff2c646 | 2014-12-08 14:54:01 -0500 | [diff] [blame] | 425 | #define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000 |
| 426 | #define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000 |
| 427 | #define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE |
| 428 | #define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) |
| 429 | #define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \ |
| 430 | CONFIG_SYS_QMAN_CENA_SIZE) |
| 431 | #define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) |
| 432 | #define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08 |
Chunhe Lan | 8e4f3ff | 2014-04-14 18:42:06 +0800 | [diff] [blame] | 433 | |
| 434 | #define CONFIG_SYS_DPAA_FMAN |
| 435 | #define CONFIG_SYS_DPAA_PME |
| 436 | #define CONFIG_SYS_PMAN |
| 437 | #define CONFIG_SYS_DPAA_DCE |
| 438 | #define CONFIG_SYS_DPAA_RMAN |
| 439 | #define CONFIG_SYS_INTERLAKEN |
| 440 | |
Chunhe Lan | 8e4f3ff | 2014-04-14 18:42:06 +0800 | [diff] [blame] | 441 | #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH) |
| 442 | #endif /* CONFIG_NOBQFMAN */ |
| 443 | |
| 444 | #ifdef CONFIG_SYS_DPAA_FMAN |
Chunhe Lan | 8e4f3ff | 2014-04-14 18:42:06 +0800 | [diff] [blame] | 445 | #define SGMII_PHY_ADDR1 0x0 |
| 446 | #define SGMII_PHY_ADDR2 0x1 |
| 447 | #define SGMII_PHY_ADDR3 0x2 |
| 448 | #define SGMII_PHY_ADDR4 0x3 |
| 449 | #define SGMII_PHY_ADDR5 0x4 |
| 450 | #define SGMII_PHY_ADDR6 0x5 |
| 451 | #define SGMII_PHY_ADDR7 0x6 |
| 452 | #define SGMII_PHY_ADDR8 0x7 |
| 453 | #define FM1_10GEC1_PHY_ADDR 0x10 |
| 454 | #define FM1_10GEC2_PHY_ADDR 0x11 |
| 455 | #define FM2_10GEC1_PHY_ADDR 0x12 |
| 456 | #define FM2_10GEC2_PHY_ADDR 0x13 |
| 457 | #define CORTINA_PHY_ADDR1 FM1_10GEC1_PHY_ADDR |
| 458 | #define CORTINA_PHY_ADDR2 FM1_10GEC2_PHY_ADDR |
| 459 | #define CORTINA_PHY_ADDR3 FM2_10GEC1_PHY_ADDR |
| 460 | #define CORTINA_PHY_ADDR4 FM2_10GEC2_PHY_ADDR |
| 461 | #endif |
| 462 | |
Chunhe Lan | 8e4f3ff | 2014-04-14 18:42:06 +0800 | [diff] [blame] | 463 | /* SATA */ |
| 464 | #ifdef CONFIG_FSL_SATA_V2 |
Chunhe Lan | 8e4f3ff | 2014-04-14 18:42:06 +0800 | [diff] [blame] | 465 | #define CONFIG_SATA1 |
| 466 | #define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR |
| 467 | #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA |
| 468 | #define CONFIG_SATA2 |
| 469 | #define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR |
| 470 | #define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA |
| 471 | |
| 472 | #define CONFIG_LBA48 |
Chunhe Lan | 8e4f3ff | 2014-04-14 18:42:06 +0800 | [diff] [blame] | 473 | #endif |
| 474 | |
| 475 | #ifdef CONFIG_FMAN_ENET |
Chunhe Lan | 8e4f3ff | 2014-04-14 18:42:06 +0800 | [diff] [blame] | 476 | #define CONFIG_ETHPRIME "FM1@DTSEC1" |
Chunhe Lan | 8e4f3ff | 2014-04-14 18:42:06 +0800 | [diff] [blame] | 477 | #endif |
| 478 | |
| 479 | /* |
| 480 | * USB |
| 481 | */ |
Chunhe Lan | 8e4f3ff | 2014-04-14 18:42:06 +0800 | [diff] [blame] | 482 | #define CONFIG_EHCI_HCD_INIT_AFTER_RESET |
Chunhe Lan | 8e4f3ff | 2014-04-14 18:42:06 +0800 | [diff] [blame] | 483 | #define CONFIG_HAS_FSL_DR_USB |
| 484 | |
Chunhe Lan | 8e4f3ff | 2014-04-14 18:42:06 +0800 | [diff] [blame] | 485 | #ifdef CONFIG_MMC |
Chunhe Lan | 8e4f3ff | 2014-04-14 18:42:06 +0800 | [diff] [blame] | 486 | #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR |
| 487 | #define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT |
Chunhe Lan | 8e4f3ff | 2014-04-14 18:42:06 +0800 | [diff] [blame] | 488 | #endif |
| 489 | |
Chunhe Lan | 8e4f3ff | 2014-04-14 18:42:06 +0800 | [diff] [blame] | 490 | |
| 491 | #define __USB_PHY_TYPE utmi |
| 492 | |
| 493 | /* |
| 494 | * T4240 has 3 DDR controllers. Default to 3-way interleaving. It can be |
| 495 | * 3way_1KB, 3way_4KB, 3way_8KB. T4160 has 2 DDR controllers. Default to 2-way |
| 496 | * interleaving. It can be cacheline, page, bank, superbank. |
| 497 | * See doc/README.fsl-ddr for details. |
| 498 | */ |
York Sun | 0fad326 | 2016-11-21 13:35:41 -0800 | [diff] [blame] | 499 | #ifdef CONFIG_ARCH_T4240 |
Chunhe Lan | 8e4f3ff | 2014-04-14 18:42:06 +0800 | [diff] [blame] | 500 | #define CTRL_INTLV_PREFERED 3way_4KB |
Chunhe Lan | 5fb0833 | 2014-05-07 10:56:18 +0800 | [diff] [blame] | 501 | #else |
| 502 | #define CTRL_INTLV_PREFERED cacheline |
| 503 | #endif |
Chunhe Lan | 8e4f3ff | 2014-04-14 18:42:06 +0800 | [diff] [blame] | 504 | |
| 505 | #define CONFIG_EXTRA_ENV_SETTINGS \ |
| 506 | "hwconfig=fsl_ddr:" \ |
| 507 | "ctlr_intlv=" __stringify(CTRL_INTLV_PREFERED) "," \ |
| 508 | "bank_intlv=auto;" \ |
| 509 | "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\ |
| 510 | "netdev=eth0\0" \ |
| 511 | "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ |
| 512 | "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \ |
| 513 | "tftpflash=tftpboot $loadaddr $uboot && " \ |
| 514 | "protect off $ubootaddr +$filesize && " \ |
| 515 | "erase $ubootaddr +$filesize && " \ |
| 516 | "cp.b $loadaddr $ubootaddr $filesize && " \ |
| 517 | "protect on $ubootaddr +$filesize && " \ |
| 518 | "cmp.b $loadaddr $ubootaddr $filesize\0" \ |
| 519 | "consoledev=ttyS0\0" \ |
| 520 | "ramdiskaddr=2000000\0" \ |
| 521 | "ramdiskfile=t4240rdb/ramdisk.uboot\0" \ |
Scott Wood | b7f4b85 | 2016-07-19 17:52:06 -0500 | [diff] [blame] | 522 | "fdtaddr=1e00000\0" \ |
Chunhe Lan | 8e4f3ff | 2014-04-14 18:42:06 +0800 | [diff] [blame] | 523 | "fdtfile=t4240rdb/t4240rdb.dtb\0" \ |
| 524 | "bdev=sda3\0" |
| 525 | |
Tom Rini | 9aed2af | 2021-08-19 14:29:00 -0400 | [diff] [blame] | 526 | #define HVBOOT \ |
Chunhe Lan | 8e4f3ff | 2014-04-14 18:42:06 +0800 | [diff] [blame] | 527 | "setenv bootargs config-addr=0x60000000; " \ |
| 528 | "bootm 0x01000000 - 0x00f00000" |
| 529 | |
Chunhe Lan | 8e4f3ff | 2014-04-14 18:42:06 +0800 | [diff] [blame] | 530 | #include <asm/fsl_secure_boot.h> |
| 531 | |
Chunhe Lan | 8e4f3ff | 2014-04-14 18:42:06 +0800 | [diff] [blame] | 532 | #endif /* __CONFIG_H */ |