blob: 2769b54601099e5e6e4eb7bf8a256a10e3aa1896 [file] [log] [blame]
Tom Rini10e47792018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0+
Marcel Ziswilerd2b64bd2017-04-01 15:43:16 -07002/*
Marcel Ziswiler07ce1a62018-05-08 17:34:11 +02003 * Copyright (c) 2016-2018 Toradex, Inc.
Marcel Ziswilerd2b64bd2017-04-01 15:43:16 -07004 */
5
6#include <common.h>
Marcel Ziswiler07ce1a62018-05-08 17:34:11 +02007#include <dm.h>
Simon Glassed38aef2020-05-10 11:40:03 -06008#include <env.h>
Simon Glass97589732020-05-10 11:40:02 -06009#include <init.h>
Simon Glass0f2af882020-05-10 11:40:05 -060010#include <log.h>
Marcel Ziswilerd2b64bd2017-04-01 15:43:16 -070011#include <asm/arch-tegra/ap.h>
12#include <asm/gpio.h>
13#include <asm/io.h>
14#include <asm/arch/gpio.h>
15#include <asm/arch/pinmux.h>
Simon Glass9d1f6192019-08-02 09:44:25 -060016#include <env_internal.h>
Marcel Ziswiler07ce1a62018-05-08 17:34:11 +020017#include <pci_tegra.h>
Simon Glassdbd79542020-05-10 11:40:11 -060018#include <linux/delay.h>
Marcel Ziswilerd2b64bd2017-04-01 15:43:16 -070019#include <power/as3722.h>
Marcel Ziswiler07ce1a62018-05-08 17:34:11 +020020#include <power/pmic.h>
Marcel Ziswilerd2b64bd2017-04-01 15:43:16 -070021
22#include "../common/tdx-common.h"
23#include "pinmux-config-apalis-tk1.h"
24
Marcel Ziswiler07ce1a62018-05-08 17:34:11 +020025#define LAN_DEV_OFF_N TEGRA_GPIO(O, 6)
26#define LAN_RESET_N TEGRA_GPIO(S, 2)
Igor Opaniukfeb8c0d2019-08-01 11:06:32 +030027#define FAN_EN TEGRA_GPIO(DD, 2)
Marcel Ziswiler07ce1a62018-05-08 17:34:11 +020028#define LAN_WAKE_N TEGRA_GPIO(O, 5)
29#ifdef CONFIG_APALIS_TK1_PCIE_EVALBOARD_INIT
30#define PEX_PERST_N TEGRA_GPIO(DD, 1) /* Apalis GPIO7 */
31#define RESET_MOCI_CTRL TEGRA_GPIO(U, 4)
32#endif /* CONFIG_APALIS_TK1_PCIE_EVALBOARD_INIT */
Marcel Ziswiler46eb7292019-08-09 13:21:46 +030033#define VCC_USBH TEGRA_GPIO(T, 6)
34#define VCC_USBH_V1_0 TEGRA_GPIO(N, 5)
35#define VCC_USBO1 TEGRA_GPIO(T, 5)
36#define VCC_USBO1_V1_0 TEGRA_GPIO(N, 4)
Marcel Ziswilerd2b64bd2017-04-01 15:43:16 -070037
38int arch_misc_init(void)
39{
40 if (readl(NV_PA_BASE_SRAM + NVBOOTINFOTABLE_BOOTTYPE) ==
Marcel Ziswiler55fb0572021-08-11 15:12:56 +020041 NVBOOTTYPE_RECOVERY) {
42 printf("USB recovery mode, attempting to boot Toradex Easy "
43 "Installer\n");
44 env_set("bootdelay", "-2");
45 env_set("defargs", "pcie_aspm=off user_debug=30");
46 env_set("fdt_high", "");
47 env_set("initrd_high", "");
48
49 env_set("setup", "env set setupargs igb_mac=${ethaddr} "
50 "consoleblank=0 no_console_suspend=1 "
51 "console=${console},${baudrate}n8 ${memargs}");
52 env_set("teziargs", "rootfstype=squashfs root=/dev/ram quiet "
53 "autoinstall");
54 env_set("vidargs", "video=HDMI-A-1:640x480-16@60D");
55 env_set("bootcmd", "run setup; env set bootargs ${defargs} "
56 "${setupargs} ${vidargs} ${teziargs}; bootm 0x80208000"
57 "#config@${soc}-${fdt_module}-${fdt_board}.dtb");
58 }
Marcel Ziswilerd2b64bd2017-04-01 15:43:16 -070059
Marcel Ziswiler46eb7292019-08-09 13:21:46 +030060 /* PCB Version Indication: V1.2 and later have GPIO_PV0 wired to GND */
61 gpio_request(TEGRA_GPIO(V, 0), "PCB Version Indication");
62 gpio_direction_input(TEGRA_GPIO(V, 0));
63 if (gpio_get_value(TEGRA_GPIO(V, 0))) {
64 /*
65 * if using the default device tree for new V1.2 and later HW,
66 * use version for older V1.0 and V1.1 HW
67 */
68 char *fdt_env = env_get("fdt_module");
69
70 if (fdt_env && !strcmp(FDT_MODULE, fdt_env)) {
71 env_set("fdt_module", FDT_MODULE_V1_0);
72 printf("patching fdt_module to " FDT_MODULE_V1_0
73 " for older V1.0 and V1.1 HW\n");
74#ifndef CONFIG_ENV_IS_NOWHERE
75 env_save();
76#endif
77 }
78
79 /* activate USB power enable GPIOs */
80 gpio_request(VCC_USBH_V1_0, "VCC_USBH");
81 gpio_direction_output(VCC_USBH_V1_0, 1);
82 gpio_request(VCC_USBO1_V1_0, "VCC_USBO1");
83 gpio_direction_output(VCC_USBO1_V1_0, 1);
84 } else {
85 /* activate USB power enable GPIOs */
86 gpio_request(VCC_USBH, "VCC_USBH");
87 gpio_direction_output(VCC_USBH, 1);
88 gpio_request(VCC_USBO1, "VCC_USBO1");
89 gpio_direction_output(VCC_USBO1, 1);
90 }
91
Marcel Ziswilerd2b64bd2017-04-01 15:43:16 -070092 return 0;
93}
94
95int checkboard(void)
96{
97 puts("Model: Toradex Apalis TK1 2GB\n");
98
99 return 0;
100}
101
102#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
Masahiro Yamadaf7ed78b2020-06-26 15:13:33 +0900103int ft_board_setup(void *blob, struct bd_info *bd)
Marcel Ziswilerd2b64bd2017-04-01 15:43:16 -0700104{
105 return ft_common_board_setup(blob, bd);
106}
107#endif
108
109/*
110 * Routine: pinmux_init
111 * Description: Do individual peripheral pinmux configs
112 */
113void pinmux_init(void)
114{
115 pinmux_clear_tristate_input_clamping();
116
117 gpio_config_table(apalis_tk1_gpio_inits,
118 ARRAY_SIZE(apalis_tk1_gpio_inits));
119
120 pinmux_config_pingrp_table(apalis_tk1_pingrps,
121 ARRAY_SIZE(apalis_tk1_pingrps));
122
123 pinmux_config_drvgrp_table(apalis_tk1_drvgrps,
124 ARRAY_SIZE(apalis_tk1_drvgrps));
125}
126
127#ifdef CONFIG_PCI_TEGRA
Marcel Ziswiler07ce1a62018-05-08 17:34:11 +0200128/* TODO: Convert to driver model */
129static int as3722_sd_enable(struct udevice *pmic, unsigned int sd)
Marcel Ziswilerd2b64bd2017-04-01 15:43:16 -0700130{
Marcel Ziswilerd2b64bd2017-04-01 15:43:16 -0700131 int err;
132
Marcel Ziswiler07ce1a62018-05-08 17:34:11 +0200133 if (sd > 6)
134 return -EINVAL;
135
136 err = pmic_clrsetbits(pmic, AS3722_SD_CONTROL, 0, 1 << sd);
Marcel Ziswilerd2b64bd2017-04-01 15:43:16 -0700137 if (err) {
Marcel Ziswiler07ce1a62018-05-08 17:34:11 +0200138 pr_err("failed to update SD control register: %d", err);
Marcel Ziswilerd2b64bd2017-04-01 15:43:16 -0700139 return err;
140 }
141
Marcel Ziswiler07ce1a62018-05-08 17:34:11 +0200142 return 0;
143}
144
145/* TODO: Convert to driver model */
146static int as3722_ldo_enable(struct udevice *pmic, unsigned int ldo)
147{
148 int err;
149 u8 ctrl_reg = AS3722_LDO_CONTROL0;
150
151 if (ldo > 11)
152 return -EINVAL;
153
154 if (ldo > 7) {
155 ctrl_reg = AS3722_LDO_CONTROL1;
156 ldo -= 8;
Marcel Ziswilerd2b64bd2017-04-01 15:43:16 -0700157 }
158
Marcel Ziswiler07ce1a62018-05-08 17:34:11 +0200159 err = pmic_clrsetbits(pmic, ctrl_reg, 0, 1 << ldo);
160 if (err) {
161 pr_err("failed to update LDO control register: %d", err);
Marcel Ziswilerd2b64bd2017-04-01 15:43:16 -0700162 return err;
163 }
164
Marcel Ziswiler07ce1a62018-05-08 17:34:11 +0200165 return 0;
166}
167
168int tegra_pcie_board_init(void)
169{
170 struct udevice *dev;
171 int ret;
172
173 ret = uclass_get_device_by_driver(UCLASS_PMIC,
Simon Glass65130cd2020-12-28 20:34:56 -0700174 DM_DRIVER_GET(pmic_as3722), &dev);
Marcel Ziswiler07ce1a62018-05-08 17:34:11 +0200175 if (ret) {
176 pr_err("failed to find AS3722 PMIC: %d\n", ret);
177 return ret;
Marcel Ziswilerd2b64bd2017-04-01 15:43:16 -0700178 }
179
Marcel Ziswiler07ce1a62018-05-08 17:34:11 +0200180 ret = as3722_sd_enable(dev, 4);
181 if (ret < 0) {
182 pr_err("failed to enable SD4: %d\n", ret);
183 return ret;
184 }
185
186 ret = as3722_sd_set_voltage(dev, 4, 0x24);
187 if (ret < 0) {
188 pr_err("failed to set SD4 voltage: %d\n", ret);
189 return ret;
Marcel Ziswilerd2b64bd2017-04-01 15:43:16 -0700190 }
191
Marcel Ziswiler07ce1a62018-05-08 17:34:11 +0200192 gpio_request(LAN_DEV_OFF_N, "LAN_DEV_OFF_N");
Marcel Ziswilerd2b64bd2017-04-01 15:43:16 -0700193 gpio_request(LAN_RESET_N, "LAN_RESET_N");
Marcel Ziswiler07ce1a62018-05-08 17:34:11 +0200194 gpio_request(LAN_WAKE_N, "LAN_WAKE_N");
195
196#ifdef CONFIG_APALIS_TK1_PCIE_EVALBOARD_INIT
197 gpio_request(PEX_PERST_N, "PEX_PERST_N");
198 gpio_request(RESET_MOCI_CTRL, "RESET_MOCI_CTRL");
199#endif /* CONFIG_APALIS_TK1_PCIE_EVALBOARD_INIT */
Marcel Ziswilerd2b64bd2017-04-01 15:43:16 -0700200
Marcel Ziswiler07ce1a62018-05-08 17:34:11 +0200201 return 0;
202}
Marcel Ziswilerd2b64bd2017-04-01 15:43:16 -0700203
Marcel Ziswiler07ce1a62018-05-08 17:34:11 +0200204void tegra_pcie_board_port_reset(struct tegra_pcie_port *port)
205{
206 int index = tegra_pcie_port_index_of_port(port);
Marcel Ziswilerd2b64bd2017-04-01 15:43:16 -0700207
Marcel Ziswiler07ce1a62018-05-08 17:34:11 +0200208 if (index == 1) { /* I210 Gigabit Ethernet Controller (On-module) */
209 struct udevice *dev;
210 int ret;
Marcel Ziswilerd2b64bd2017-04-01 15:43:16 -0700211
Marcel Ziswiler07ce1a62018-05-08 17:34:11 +0200212 ret = uclass_get_device_by_driver(UCLASS_PMIC,
Simon Glass65130cd2020-12-28 20:34:56 -0700213 DM_DRIVER_GET(pmic_as3722),
Marcel Ziswiler07ce1a62018-05-08 17:34:11 +0200214 &dev);
215 if (ret) {
216 debug("%s: Failed to find PMIC\n", __func__);
217 return;
218 }
Marcel Ziswilerd2b64bd2017-04-01 15:43:16 -0700219
Marcel Ziswiler07ce1a62018-05-08 17:34:11 +0200220 /* Reset I210 Gigabit Ethernet Controller */
221 gpio_direction_output(LAN_RESET_N, 0);
Marcel Ziswilerd2b64bd2017-04-01 15:43:16 -0700222
Marcel Ziswiler07ce1a62018-05-08 17:34:11 +0200223 /*
224 * Make sure we don't get any back feeding from DEV_OFF_N resp.
225 * LAN_WAKE_N
226 */
227 gpio_direction_output(LAN_DEV_OFF_N, 0);
228 gpio_direction_output(LAN_WAKE_N, 0);
Marcel Ziswilerd2b64bd2017-04-01 15:43:16 -0700229
Marcel Ziswiler07ce1a62018-05-08 17:34:11 +0200230 /* Make sure LDO9 and LDO10 are initially enabled @ 0V */
231 ret = as3722_ldo_enable(dev, 9);
232 if (ret < 0) {
233 pr_err("failed to enable LDO9: %d\n", ret);
234 return;
235 }
236 ret = as3722_ldo_enable(dev, 10);
237 if (ret < 0) {
238 pr_err("failed to enable LDO10: %d\n", ret);
239 return;
240 }
241 ret = as3722_ldo_set_voltage(dev, 9, 0x80);
242 if (ret < 0) {
243 pr_err("failed to set LDO9 voltage: %d\n", ret);
244 return;
245 }
246 ret = as3722_ldo_set_voltage(dev, 10, 0x80);
247 if (ret < 0) {
248 pr_err("failed to set LDO10 voltage: %d\n", ret);
249 return;
250 }
Marcel Ziswilerd2b64bd2017-04-01 15:43:16 -0700251
Marcel Ziswiler07ce1a62018-05-08 17:34:11 +0200252 /* Make sure controller gets enabled by disabling DEV_OFF_N */
253 gpio_set_value(LAN_DEV_OFF_N, 1);
Marcel Ziswilerd2b64bd2017-04-01 15:43:16 -0700254
Marcel Ziswiler07ce1a62018-05-08 17:34:11 +0200255 /*
256 * Enable LDO9 and LDO10 for +V3.3_ETH on patched prototype
257 * V1.0A and sample V1.0B and newer modules
258 */
259 ret = as3722_ldo_set_voltage(dev, 9, 0xff);
260 if (ret < 0) {
261 pr_err("failed to set LDO9 voltage: %d\n", ret);
262 return;
263 }
264 ret = as3722_ldo_set_voltage(dev, 10, 0xff);
265 if (ret < 0) {
266 pr_err("failed to set LDO10 voltage: %d\n", ret);
267 return;
268 }
Marcel Ziswilerd2b64bd2017-04-01 15:43:16 -0700269
Marcel Ziswiler07ce1a62018-05-08 17:34:11 +0200270 /*
271 * Must be asserted for 100 ms after power and clocks are stable
272 */
273 mdelay(100);
274
275 gpio_set_value(LAN_RESET_N, 1);
276 } else if (index == 0) { /* Apalis PCIe */
277#ifdef CONFIG_APALIS_TK1_PCIE_EVALBOARD_INIT
278 /*
279 * Reset PLX PEX 8605 PCIe Switch plus PCIe devices on Apalis
280 * Evaluation Board
281 */
282 gpio_direction_output(PEX_PERST_N, 0);
283 gpio_direction_output(RESET_MOCI_CTRL, 0);
284
285 /*
286 * Must be asserted for 100 ms after power and clocks are stable
287 */
288 mdelay(100);
289
290 gpio_set_value(PEX_PERST_N, 1);
291 /*
292 * Err_5: PEX_REFCLK_OUTpx/nx Clock Outputs is not Guaranteed
293 * Until 900 us After PEX_PERST# De-assertion
294 */
295 mdelay(1);
296 gpio_set_value(RESET_MOCI_CTRL, 1);
297#endif /* CONFIG_APALIS_TK1_PCIE_EVALBOARD_INIT */
298 }
Marcel Ziswilerd2b64bd2017-04-01 15:43:16 -0700299}
300#endif /* CONFIG_PCI_TEGRA */
Gerard Salvatella108d7392018-11-19 15:54:10 +0100301
302/*
Igor Opaniukfeb8c0d2019-08-01 11:06:32 +0300303 * Enable/start PWM CPU fan
304 */
305void start_cpu_fan(void)
306{
307 gpio_request(FAN_EN, "FAN_EN");
308 gpio_direction_output(FAN_EN, 1);
309}
310
311/*
Gerard Salvatella108d7392018-11-19 15:54:10 +0100312 * Backlight off before OS handover
313 */
314void board_preboot_os(void)
315{
316 gpio_request(TEGRA_GPIO(BB, 5), "BL_ON");
317 gpio_direction_output(TEGRA_GPIO(BB, 5), 0);
318}