Tom Rini | 10e4779 | 2018-05-06 17:58:06 -0400 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0 */ |
Rick Chen | 76c0a24 | 2017-12-26 13:55:51 +0800 | [diff] [blame] | 2 | /* |
| 3 | * Copyright (C) 2017 Andes Technology Corporation |
| 4 | * Rick Chen, Andes Technology Corporation <rick@andestech.com> |
| 5 | * |
Rick Chen | 76c0a24 | 2017-12-26 13:55:51 +0800 | [diff] [blame] | 6 | */ |
| 7 | #ifndef __ASM_RISCV_IO_H |
| 8 | #define __ASM_RISCV_IO_H |
| 9 | |
| 10 | #ifdef __KERNEL__ |
| 11 | |
| 12 | #include <linux/types.h> |
Lukas Auer | 78da26d | 2018-11-22 11:26:18 +0100 | [diff] [blame] | 13 | #include <asm/barrier.h> |
Rick Chen | 76c0a24 | 2017-12-26 13:55:51 +0800 | [diff] [blame] | 14 | #include <asm/byteorder.h> |
| 15 | |
| 16 | static inline void sync(void) |
| 17 | { |
| 18 | } |
| 19 | |
Rick Chen | 76c0a24 | 2017-12-26 13:55:51 +0800 | [diff] [blame] | 20 | #ifdef CONFIG_ARCH_MAP_SYSMEM |
| 21 | static inline void *map_sysmem(phys_addr_t paddr, unsigned long len) |
| 22 | { |
| 23 | if (paddr < PHYS_SDRAM_0_SIZE + PHYS_SDRAM_1_SIZE) |
| 24 | paddr = paddr | 0x40000000; |
| 25 | return (void *)(uintptr_t)paddr; |
| 26 | } |
| 27 | |
| 28 | static inline void *unmap_sysmem(const void *vaddr) |
| 29 | { |
| 30 | phys_addr_t paddr = (phys_addr_t)vaddr; |
| 31 | |
| 32 | paddr = paddr & ~0x40000000; |
| 33 | return (void *)(uintptr_t)paddr; |
| 34 | } |
| 35 | |
| 36 | static inline phys_addr_t map_to_sysmem(const void *ptr) |
| 37 | { |
| 38 | return (phys_addr_t)(uintptr_t)ptr; |
| 39 | } |
| 40 | #endif |
| 41 | |
Rick Chen | 76c0a24 | 2017-12-26 13:55:51 +0800 | [diff] [blame] | 42 | /* |
| 43 | * Generic virtual read/write. Note that we don't support half-word |
| 44 | * read/writes. We define __arch_*[bl] here, and leave __arch_*w |
| 45 | * to the architecture specific code. |
| 46 | */ |
Nick Hu | 579f12b | 2021-10-18 11:50:05 +0800 | [diff] [blame] | 47 | #define __arch_getb(a) (*(volatile unsigned char *)(a)) |
| 48 | #define __arch_getw(a) (*(volatile unsigned short *)(a)) |
| 49 | #define __arch_getl(a) (*(volatile unsigned int *)(a)) |
| 50 | #define __arch_getq(a) (*(volatile unsigned long long *)(a)) |
Rick Chen | 76c0a24 | 2017-12-26 13:55:51 +0800 | [diff] [blame] | 51 | |
Nick Hu | 579f12b | 2021-10-18 11:50:05 +0800 | [diff] [blame] | 52 | #define __arch_putb(v, a) (*(volatile unsigned char *)(a) = (v)) |
| 53 | #define __arch_putw(v, a) (*(volatile unsigned short *)(a) = (v)) |
| 54 | #define __arch_putl(v, a) (*(volatile unsigned int *)(a) = (v)) |
| 55 | #define __arch_putq(v, a) (*(volatile unsigned long long *)(a) = (v)) |
Rick Chen | 76c0a24 | 2017-12-26 13:55:51 +0800 | [diff] [blame] | 56 | |
| 57 | #define __raw_writeb(v, a) __arch_putb(v, a) |
| 58 | #define __raw_writew(v, a) __arch_putw(v, a) |
| 59 | #define __raw_writel(v, a) __arch_putl(v, a) |
| 60 | #define __raw_writeq(v, a) __arch_putq(v, a) |
| 61 | |
| 62 | #define __raw_readb(a) __arch_getb(a) |
| 63 | #define __raw_readw(a) __arch_getw(a) |
| 64 | #define __raw_readl(a) __arch_getl(a) |
| 65 | #define __raw_readq(a) __arch_getq(a) |
| 66 | |
Wei Fu | 2f5b807 | 2021-10-24 00:31:12 +0800 | [diff] [blame] | 67 | /* adding for cadence_qspi_apb.c */ |
| 68 | #define memcpy_fromio(a, c, l) memcpy((a), (c), (l)) |
| 69 | #define memcpy_toio(c, a, l) memcpy((c), (a), (l)) |
| 70 | |
Lukas Auer | 78da26d | 2018-11-22 11:26:18 +0100 | [diff] [blame] | 71 | #define dmb() mb() |
| 72 | #define __iormb() rmb() |
| 73 | #define __iowmb() wmb() |
Rick Chen | 76c0a24 | 2017-12-26 13:55:51 +0800 | [diff] [blame] | 74 | |
| 75 | static inline void writeb(u8 val, volatile void __iomem *addr) |
| 76 | { |
| 77 | __iowmb(); |
| 78 | __arch_putb(val, addr); |
| 79 | } |
| 80 | |
| 81 | static inline void writew(u16 val, volatile void __iomem *addr) |
| 82 | { |
| 83 | __iowmb(); |
| 84 | __arch_putw(val, addr); |
| 85 | } |
| 86 | |
| 87 | static inline void writel(u32 val, volatile void __iomem *addr) |
| 88 | { |
| 89 | __iowmb(); |
| 90 | __arch_putl(val, addr); |
| 91 | } |
| 92 | |
| 93 | static inline void writeq(u64 val, volatile void __iomem *addr) |
| 94 | { |
| 95 | __iowmb(); |
| 96 | __arch_putq(val, addr); |
| 97 | } |
| 98 | |
| 99 | static inline u8 readb(const volatile void __iomem *addr) |
| 100 | { |
| 101 | u8 val; |
| 102 | |
| 103 | val = __arch_getb(addr); |
| 104 | __iormb(); |
| 105 | return val; |
| 106 | } |
| 107 | |
| 108 | static inline u16 readw(const volatile void __iomem *addr) |
| 109 | { |
| 110 | u16 val; |
| 111 | |
| 112 | val = __arch_getw(addr); |
| 113 | __iormb(); |
| 114 | return val; |
| 115 | } |
| 116 | |
| 117 | static inline u32 readl(const volatile void __iomem *addr) |
| 118 | { |
| 119 | u32 val; |
| 120 | |
| 121 | val = __arch_getl(addr); |
| 122 | __iormb(); |
| 123 | return val; |
| 124 | } |
| 125 | |
| 126 | static inline u64 readq(const volatile void __iomem *addr) |
| 127 | { |
Lukas Auer | e429a1e | 2018-11-22 11:26:17 +0100 | [diff] [blame] | 128 | u64 val; |
Rick Chen | 76c0a24 | 2017-12-26 13:55:51 +0800 | [diff] [blame] | 129 | |
| 130 | val = __arch_getq(addr); |
| 131 | __iormb(); |
| 132 | return val; |
| 133 | } |
| 134 | |
| 135 | /* |
| 136 | * The compiler seems to be incapable of optimising constants |
| 137 | * properly. Spell it out to the compiler in some cases. |
| 138 | * These are only valid for small values of "off" (< 1<<12) |
| 139 | */ |
| 140 | #define __raw_base_writeb(val, base, off) __arch_base_putb(val, base, off) |
| 141 | #define __raw_base_writew(val, base, off) __arch_base_putw(val, base, off) |
| 142 | #define __raw_base_writel(val, base, off) __arch_base_putl(val, base, off) |
| 143 | |
| 144 | #define __raw_base_readb(base, off) __arch_base_getb(base, off) |
| 145 | #define __raw_base_readw(base, off) __arch_base_getw(base, off) |
| 146 | #define __raw_base_readl(base, off) __arch_base_getl(base, off) |
| 147 | |
| 148 | #define out_arch(type, endian, a, v) __raw_write##type(cpu_to_##endian(v), a) |
| 149 | #define in_arch(type, endian, a) endian##_to_cpu(__raw_read##type(a)) |
| 150 | |
| 151 | #define out_le32(a, v) out_arch(l, le32, a, v) |
| 152 | #define out_le16(a, v) out_arch(w, le16, a, v) |
| 153 | |
| 154 | #define in_le32(a) in_arch(l, le32, a) |
| 155 | #define in_le16(a) in_arch(w, le16, a) |
| 156 | |
| 157 | #define out_be32(a, v) out_arch(l, be32, a, v) |
| 158 | #define out_be16(a, v) out_arch(w, be16, a, v) |
| 159 | |
| 160 | #define in_be32(a) in_arch(l, be32, a) |
| 161 | #define in_be16(a) in_arch(w, be16, a) |
| 162 | |
| 163 | #define out_8(a, v) __raw_writeb(v, a) |
| 164 | #define in_8(a) __raw_readb(a) |
| 165 | |
| 166 | /* |
| 167 | * Clear and set bits in one shot. These macros can be used to clear and |
| 168 | * set multiple bits in a register using a single call. These macros can |
| 169 | * also be used to set a multiple-bit bit pattern using a mask, by |
| 170 | * specifying the mask in the 'clear' parameter and the new bit pattern |
| 171 | * in the 'set' parameter. |
| 172 | */ |
| 173 | |
| 174 | #define clrbits(type, addr, clear) \ |
| 175 | out_##type((addr), in_##type(addr) & ~(clear)) |
| 176 | |
| 177 | #define setbits(type, addr, set) \ |
| 178 | out_##type((addr), in_##type(addr) | (set)) |
| 179 | |
| 180 | #define clrsetbits(type, addr, clear, set) \ |
| 181 | out_##type((addr), (in_##type(addr) & ~(clear)) | (set)) |
| 182 | |
| 183 | #define clrbits_be32(addr, clear) clrbits(be32, addr, clear) |
| 184 | #define setbits_be32(addr, set) setbits(be32, addr, set) |
| 185 | #define clrsetbits_be32(addr, clear, set) clrsetbits(be32, addr, clear, set) |
| 186 | |
| 187 | #define clrbits_le32(addr, clear) clrbits(le32, addr, clear) |
| 188 | #define setbits_le32(addr, set) setbits(le32, addr, set) |
| 189 | #define clrsetbits_le32(addr, clear, set) clrsetbits(le32, addr, clear, set) |
| 190 | |
| 191 | #define clrbits_be16(addr, clear) clrbits(be16, addr, clear) |
| 192 | #define setbits_be16(addr, set) setbits(be16, addr, set) |
| 193 | #define clrsetbits_be16(addr, clear, set) clrsetbits(be16, addr, clear, set) |
| 194 | |
| 195 | #define clrbits_le16(addr, clear) clrbits(le16, addr, clear) |
| 196 | #define setbits_le16(addr, set) setbits(le16, addr, set) |
| 197 | #define clrsetbits_le16(addr, clear, set) clrsetbits(le16, addr, clear, set) |
| 198 | |
| 199 | #define clrbits_8(addr, clear) clrbits(8, addr, clear) |
| 200 | #define setbits_8(addr, set) setbits(8, addr, set) |
| 201 | #define clrsetbits_8(addr, clear, set) clrsetbits(8, addr, clear, set) |
| 202 | |
| 203 | /* |
| 204 | * Now, pick up the machine-defined IO definitions |
| 205 | * #include <asm/arch/io.h> |
| 206 | */ |
| 207 | |
| 208 | /* |
| 209 | * IO port access primitives |
| 210 | * ------------------------- |
| 211 | * |
| 212 | * The NDS32 doesn't have special IO access instructions just like ARM; |
| 213 | * all IO is memory mapped. |
| 214 | * Note that these are defined to perform little endian accesses |
| 215 | * only. Their primary purpose is to access PCI and ISA peripherals. |
| 216 | * |
| 217 | * Note that for a big endian machine, this implies that the following |
| 218 | * big endian mode connectivity is in place, as described by numerious |
| 219 | * ARM documents: |
| 220 | * |
| 221 | * PCI: D0-D7 D8-D15 D16-D23 D24-D31 |
| 222 | * ARM: D24-D31 D16-D23 D8-D15 D0-D7 |
| 223 | * |
| 224 | * The machine specific io.h include defines __io to translate an "IO" |
| 225 | * address to a memory address. |
| 226 | * |
| 227 | * Note that we prevent GCC re-ordering or caching values in expressions |
| 228 | * by introducing sequence points into the in*() definitions. Note that |
| 229 | * __raw_* do not guarantee this behaviour. |
| 230 | * |
| 231 | * The {in,out}[bwl] macros are for emulating x86-style PCI/ISA IO space. |
| 232 | */ |
| 233 | #ifdef __io |
| 234 | #define outb(v, p) __raw_writeb(v, __io(p)) |
| 235 | #define outw(v, p) __raw_writew(cpu_to_le16(v), __io(p)) |
| 236 | #define outl(v, p) __raw_writel(cpu_to_le32(v), __io(p)) |
| 237 | |
| 238 | #define inb(p) ({ unsigned int __v = __raw_readb(__io(p)); __v; }) |
| 239 | #define inw(p) ({ unsigned int __v = le16_to_cpu(__raw_readw(__io(p))); __v; }) |
| 240 | #define inl(p) ({ unsigned int __v = le32_to_cpu(__raw_readl(__io(p))); __v; }) |
| 241 | |
| 242 | #define outsb(p, d, l) writesb(__io(p), d, l) |
| 243 | #define outsw(p, d, l) writesw(__io(p), d, l) |
| 244 | #define outsl(p, d, l) writesl(__io(p), d, l) |
| 245 | |
| 246 | #define insb(p, d, l) readsb(__io(p), d, l) |
| 247 | #define insw(p, d, l) readsw(__io(p), d, l) |
| 248 | #define insl(p, d, l) readsl(__io(p), d, l) |
| 249 | |
| 250 | static inline void readsb(unsigned int *addr, void *data, int bytelen) |
| 251 | { |
| 252 | unsigned char *ptr; |
| 253 | unsigned char *ptr2; |
| 254 | |
| 255 | ptr = (unsigned char *)addr; |
| 256 | ptr2 = (unsigned char *)data; |
| 257 | |
| 258 | while (bytelen) { |
| 259 | *ptr2 = *ptr; |
| 260 | ptr2++; |
| 261 | bytelen--; |
| 262 | } |
| 263 | } |
| 264 | |
| 265 | static inline void readsw(unsigned int *addr, void *data, int wordlen) |
| 266 | { |
| 267 | unsigned short *ptr; |
| 268 | unsigned short *ptr2; |
| 269 | |
| 270 | ptr = (unsigned short *)addr; |
| 271 | ptr2 = (unsigned short *)data; |
| 272 | |
| 273 | while (wordlen) { |
| 274 | *ptr2 = *ptr; |
| 275 | ptr2++; |
| 276 | wordlen--; |
| 277 | } |
| 278 | } |
| 279 | |
| 280 | static inline void readsl(unsigned int *addr, void *data, int longlen) |
| 281 | { |
| 282 | unsigned int *ptr; |
| 283 | unsigned int *ptr2; |
| 284 | |
| 285 | ptr = (unsigned int *)addr; |
| 286 | ptr2 = (unsigned int *)data; |
| 287 | |
| 288 | while (longlen) { |
| 289 | *ptr2 = *ptr; |
| 290 | ptr2++; |
| 291 | longlen--; |
| 292 | } |
| 293 | } |
| 294 | |
| 295 | static inline void writesb(unsigned int *addr, const void *data, int bytelen) |
| 296 | { |
| 297 | unsigned char *ptr; |
| 298 | unsigned char *ptr2; |
| 299 | |
| 300 | ptr = (unsigned char *)addr; |
| 301 | ptr2 = (unsigned char *)data; |
| 302 | |
| 303 | while (bytelen) { |
| 304 | *ptr = *ptr2; |
| 305 | ptr2++; |
| 306 | bytelen--; |
| 307 | } |
| 308 | } |
| 309 | |
| 310 | static inline void writesw(unsigned int *addr, const void *data, int wordlen) |
| 311 | { |
| 312 | unsigned short *ptr; |
| 313 | unsigned short *ptr2; |
| 314 | |
| 315 | ptr = (unsigned short *)addr; |
| 316 | ptr2 = (unsigned short *)data; |
| 317 | |
| 318 | while (wordlen) { |
| 319 | *ptr = *ptr2; |
| 320 | ptr2++; |
| 321 | wordlen--; |
| 322 | } |
| 323 | } |
| 324 | |
| 325 | static inline void writesl(unsigned int *addr, const void *data, int longlen) |
| 326 | { |
| 327 | unsigned int *ptr; |
| 328 | unsigned int *ptr2; |
| 329 | |
| 330 | ptr = (unsigned int *)addr; |
| 331 | ptr2 = (unsigned int *)data; |
| 332 | |
| 333 | while (longlen) { |
| 334 | *ptr = *ptr2; |
| 335 | ptr2++; |
| 336 | longlen--; |
| 337 | } |
| 338 | } |
| 339 | #endif |
| 340 | |
| 341 | #define outb_p(val, port) outb((val), (port)) |
| 342 | #define outw_p(val, port) outw((val), (port)) |
| 343 | #define outl_p(val, port) outl((val), (port)) |
| 344 | #define inb_p(port) inb((port)) |
| 345 | #define inw_p(port) inw((port)) |
| 346 | #define inl_p(port) inl((port)) |
| 347 | |
| 348 | #define outsb_p(port, from, len) outsb(port, from, len) |
| 349 | #define outsw_p(port, from, len) outsw(port, from, len) |
| 350 | #define outsl_p(port, from, len) outsl(port, from, len) |
| 351 | #define insb_p(port, to, len) insb(port, to, len) |
| 352 | #define insw_p(port, to, len) insw(port, to, len) |
| 353 | #define insl_p(port, to, len) insl(port, to, len) |
| 354 | |
| 355 | /* |
| 356 | * DMA-consistent mapping functions. These allocate/free a region of |
| 357 | * uncached, unwrite-buffered mapped memory space for use with DMA |
| 358 | * devices. This is the "generic" version. The PCI specific version |
| 359 | * is in pci.h |
| 360 | */ |
| 361 | |
| 362 | /* |
| 363 | * String version of IO memory access ops: |
| 364 | */ |
| 365 | |
| 366 | /* |
| 367 | * If this architecture has PCI memory IO, then define the read/write |
| 368 | * macros. These should only be used with the cookie passed from |
| 369 | * ioremap. |
| 370 | */ |
| 371 | #ifdef __mem_pci |
| 372 | |
| 373 | #define readb(c) ({ unsigned int __v = \ |
| 374 | __raw_readb(__mem_pci(c)); __v; }) |
| 375 | #define readw(c) ({ unsigned int __v = \ |
| 376 | le16_to_cpu(__raw_readw(__mem_pci(c))); __v; }) |
| 377 | #define readl(c) ({ unsigned int __v = \ |
| 378 | le32_to_cpu(__raw_readl(__mem_pci(c))); __v; }) |
| 379 | |
| 380 | #define writeb(v, c) __raw_writeb(v, __mem_pci(c)) |
| 381 | #define writew(v, c) __raw_writew(cpu_to_le16(v), __mem_pci(c)) |
| 382 | #define writel(v, c) __raw_writel(cpu_to_le32(v), __mem_pci(c)) |
| 383 | |
| 384 | #define memset_io(c, v, l) _memset_io(__mem_pci(c), (v), (l)) |
| 385 | #define memcpy_fromio(a, c, l) _memcpy_fromio((a), __mem_pci(c), (l)) |
| 386 | #define memcpy_toio(c, a, l) _memcpy_toio(__mem_pci(c), (a), (l)) |
| 387 | |
| 388 | #define eth_io_copy_and_sum(s, c, l, b) \ |
| 389 | eth_copy_and_sum((s), __mem_pci(c), (l), (b)) |
| 390 | |
Rick Chen | 69ae630 | 2018-02-12 11:17:47 +0800 | [diff] [blame] | 391 | static inline int check_signature(ulong io_addr, const uchar *s, int len) |
Rick Chen | 76c0a24 | 2017-12-26 13:55:51 +0800 | [diff] [blame] | 392 | { |
| 393 | int retval = 0; |
| 394 | |
| 395 | do { |
Rick Chen | 69ae630 | 2018-02-12 11:17:47 +0800 | [diff] [blame] | 396 | if (readb(io_addr) != *s) |
Rick Chen | 76c0a24 | 2017-12-26 13:55:51 +0800 | [diff] [blame] | 397 | goto out; |
| 398 | io_addr++; |
Rick Chen | 69ae630 | 2018-02-12 11:17:47 +0800 | [diff] [blame] | 399 | s++; |
| 400 | len--; |
| 401 | } while (len); |
Rick Chen | 76c0a24 | 2017-12-26 13:55:51 +0800 | [diff] [blame] | 402 | retval = 1; |
| 403 | out: |
| 404 | return retval; |
| 405 | } |
| 406 | #endif /* __mem_pci */ |
| 407 | |
| 408 | /* |
| 409 | * If this architecture has ISA IO, then define the isa_read/isa_write |
| 410 | * macros. |
| 411 | */ |
| 412 | #ifdef __mem_isa |
| 413 | |
| 414 | #define isa_readb(addr) __raw_readb(__mem_isa(addr)) |
| 415 | #define isa_readw(addr) __raw_readw(__mem_isa(addr)) |
| 416 | #define isa_readl(addr) __raw_readl(__mem_isa(addr)) |
| 417 | #define isa_writeb(val, addr) __raw_writeb(val, __mem_isa(addr)) |
| 418 | #define isa_writew(val, addr) __raw_writew(val, __mem_isa(addr)) |
| 419 | #define isa_writel(val, addr) __raw_writel(val, __mem_isa(addr)) |
| 420 | #define isa_memset_io(a, b, c) _memset_io(__mem_isa(a), (b), (c)) |
| 421 | #define isa_memcpy_fromio(a, b, c) _memcpy_fromio((a), __mem_isa(b), (c)) |
| 422 | #define isa_memcpy_toio(a, b, c) _memcpy_toio(__mem_isa((a)), (b), (c)) |
| 423 | |
| 424 | #define isa_eth_io_copy_and_sum(a, b, c, d) \ |
| 425 | eth_copy_and_sum((a), __mem_isa(b), (c), (d)) |
| 426 | |
| 427 | static inline int |
Rick Chen | 69ae630 | 2018-02-12 11:17:47 +0800 | [diff] [blame] | 428 | isa_check_signature(ulong io_addr, const uchar *s, int len) |
Rick Chen | 76c0a24 | 2017-12-26 13:55:51 +0800 | [diff] [blame] | 429 | { |
| 430 | int retval = 0; |
| 431 | |
| 432 | do { |
Rick Chen | 69ae630 | 2018-02-12 11:17:47 +0800 | [diff] [blame] | 433 | if (isa_readb(io_addr) != *s) |
Rick Chen | 76c0a24 | 2017-12-26 13:55:51 +0800 | [diff] [blame] | 434 | goto out; |
| 435 | io_addr++; |
Rick Chen | 69ae630 | 2018-02-12 11:17:47 +0800 | [diff] [blame] | 436 | s++; |
| 437 | len--; |
| 438 | } while (len); |
Rick Chen | 76c0a24 | 2017-12-26 13:55:51 +0800 | [diff] [blame] | 439 | retval = 1; |
| 440 | out: |
| 441 | return retval; |
| 442 | } |
| 443 | |
| 444 | #else /* __mem_isa */ |
| 445 | |
| 446 | #define isa_readb(addr) (__readwrite_bug("isa_readb"), 0) |
| 447 | #define isa_readw(addr) (__readwrite_bug("isa_readw"), 0) |
| 448 | #define isa_readl(addr) (__readwrite_bug("isa_readl"), 0) |
| 449 | #define isa_writeb(val, addr) __readwrite_bug("isa_writeb") |
| 450 | #define isa_writew(val, addr) __readwrite_bug("isa_writew") |
| 451 | #define isa_writel(val, addr) __readwrite_bug("isa_writel") |
| 452 | #define isa_memset_io(a, b, c) __readwrite_bug("isa_memset_io") |
| 453 | #define isa_memcpy_fromio(a, b, c) __readwrite_bug("isa_memcpy_fromio") |
| 454 | #define isa_memcpy_toio(a, b, c) __readwrite_bug("isa_memcpy_toio") |
| 455 | |
| 456 | #define isa_eth_io_copy_and_sum(a, b, c, d) \ |
| 457 | __readwrite_bug("isa_eth_io_copy_and_sum") |
| 458 | |
| 459 | #define isa_check_signature(io, sig, len) (0) |
| 460 | |
| 461 | #endif /* __mem_isa */ |
| 462 | #endif /* __KERNEL__ */ |
Lukas Auer | 09db5fc | 2018-11-22 11:26:19 +0100 | [diff] [blame] | 463 | |
| 464 | #include <asm-generic/io.h> |
| 465 | |
Rick Chen | 76c0a24 | 2017-12-26 13:55:51 +0800 | [diff] [blame] | 466 | #endif /* __ASM_RISCV_IO_H */ |