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Tom Rini10e47792018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0+
Stefan Roesee463bf32015-01-19 11:33:42 +01002/*
Stefan Roese44e7ebd2016-01-07 14:09:09 +01003 * Copyright (C) 2014-2016 Stefan Roese <sr@denx.de>
Stefan Roesee463bf32015-01-19 11:33:42 +01004 */
5
6#include <common.h>
Marek Behún90555af2022-02-17 13:54:42 +01007#include <cpu_func.h>
Stefan Roese83097cf2015-11-25 07:37:00 +01008#include <dm.h>
Stefan Roese83097cf2015-11-25 07:37:00 +01009#include <fdtdec.h>
Simon Glassf11478f2019-12-28 10:45:07 -070010#include <hang.h>
Pali Rohárcf97b822021-07-23 11:14:29 +020011#include <image.h>
Simon Glass97589732020-05-10 11:40:02 -060012#include <init.h>
Simon Glass0f2af882020-05-10 11:40:05 -060013#include <log.h>
Stefan Roesee463bf32015-01-19 11:33:42 +010014#include <spl.h>
Simon Glass3ba929a2020-10-30 21:38:53 -060015#include <asm/global_data.h>
Stefan Roesee463bf32015-01-19 11:33:42 +010016#include <asm/io.h>
17#include <asm/arch/cpu.h>
18#include <asm/arch/soc.h>
19
Simon Glassb58bfe02021-08-08 12:20:09 -060020#if defined(CONFIG_SPL_SPI_FLASH_SUPPORT) || defined(CONFIG_SPL_MMC) || \
Simon Glass081a45a2021-08-08 12:20:17 -060021 defined(CONFIG_SPL_SATA)
Pali Rohárcf97b822021-07-23 11:14:29 +020022
23/*
24 * When loading U-Boot via SPL from SPI NOR, CONFIG_SYS_SPI_U_BOOT_OFFS must
25 * point to the offset of kwbimage main header which is always at offset zero
26 * (defined by BootROM). Therefore other values of CONFIG_SYS_SPI_U_BOOT_OFFS
27 * makes U-Boot non-bootable.
28 */
29#ifdef CONFIG_SPL_SPI_FLASH_SUPPORT
30#if defined(CONFIG_SYS_SPI_U_BOOT_OFFS) && CONFIG_SYS_SPI_U_BOOT_OFFS != 0
31#error CONFIG_SYS_SPI_U_BOOT_OFFS must be set to 0
32#endif
33#endif
34
35/*
36 * When loading U-Boot via SPL from eMMC (in Marvell terminology SDIO), the
37 * kwbimage main header is stored at sector 0. U-Boot SPL needs to parse this
38 * header and figure out at which sector the U-Boot proper binary is stored.
39 * Partition booting is therefore not supported and CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR
40 * and CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_DATA_PART_OFFSET need to point to the
41 * kwbimage main header.
42 */
Simon Glassb58bfe02021-08-08 12:20:09 -060043#ifdef CONFIG_SPL_MMC
Pali Rohárcf97b822021-07-23 11:14:29 +020044#ifdef CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION
45#error CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION is unsupported
46#endif
47#if defined(CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR) && CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR != 0
48#error CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR must be set to 0
49#endif
Marek Behún3a7bbd82022-01-14 14:31:45 +010050#if defined(CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_DATA_PART_OFFSET) && \
51 CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_DATA_PART_OFFSET != 0
Pali Rohárcf97b822021-07-23 11:14:29 +020052#error CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_DATA_PART_OFFSET must be set to 0
53#endif
54#endif
55
56/*
57 * When loading U-Boot via SPL from SATA disk, the kwbimage main header is
58 * stored at sector 1. Therefore CONFIG_SPL_SATA_RAW_U_BOOT_SECTOR must be
59 * set to 1. Otherwise U-Boot SPL would not be able to load U-Boot proper.
60 */
Simon Glass081a45a2021-08-08 12:20:17 -060061#ifdef CONFIG_SPL_SATA
Marek Behún3a7bbd82022-01-14 14:31:45 +010062#if !defined(CONFIG_SPL_SATA_RAW_U_BOOT_USE_SECTOR) || \
63 !defined(CONFIG_SPL_SATA_RAW_U_BOOT_SECTOR) || CONFIG_SPL_SATA_RAW_U_BOOT_SECTOR != 1
Pali Rohárcf97b822021-07-23 11:14:29 +020064#error CONFIG_SPL_SATA_RAW_U_BOOT_SECTOR must be set to 1
65#endif
66#endif
67
68/* Boot Type - block ID */
69#define IBR_HDR_I2C_ID 0x4D
70#define IBR_HDR_SPI_ID 0x5A
71#define IBR_HDR_NAND_ID 0x8B
72#define IBR_HDR_SATA_ID 0x78
73#define IBR_HDR_PEX_ID 0x9C
74#define IBR_HDR_UART_ID 0x69
75#define IBR_HDR_SDIO_ID 0xAE
76
Pali Rohár0f7df222021-10-22 12:41:10 +020077/* Structure of the main header, version 1 (Armada 370/XP/375/38x/39x) */
Pali Rohárcf97b822021-07-23 11:14:29 +020078struct kwbimage_main_hdr_v1 {
Marek Behún031d1722022-01-14 14:31:43 +010079 u8 blockid; /* 0x0 */
80 u8 flags; /* 0x1 */
81 u16 nandpagesize; /* 0x2-0x3 */
82 u32 blocksize; /* 0x4-0x7 */
83 u8 version; /* 0x8 */
84 u8 headersz_msb; /* 0x9 */
85 u16 headersz_lsb; /* 0xA-0xB */
86 u32 srcaddr; /* 0xC-0xF */
87 u32 destaddr; /* 0x10-0x13 */
88 u32 execaddr; /* 0x14-0x17 */
89 u8 options; /* 0x18 */
90 u8 nandblocksize; /* 0x19 */
91 u8 nandbadblklocation; /* 0x1A */
92 u8 reserved4; /* 0x1B */
93 u16 reserved5; /* 0x1C-0x1D */
94 u8 ext; /* 0x1E */
95 u8 checksum; /* 0x1F */
Pali Rohárcf97b822021-07-23 11:14:29 +020096} __packed;
97
Simon Glassb58bfe02021-08-08 12:20:09 -060098#ifdef CONFIG_SPL_MMC
Pali Rohárcf97b822021-07-23 11:14:29 +020099u32 spl_mmc_boot_mode(const u32 boot_device)
100{
101 return MMCSD_MODE_RAW;
102}
103#endif
104
Pali Rohár82420562022-01-14 14:31:41 +0100105static u32 checksum32(void *start, u32 len)
106{
107 u32 csum = 0;
108 u32 *p = start;
109
110 while (len > 0) {
111 csum += *p++;
112 len -= sizeof(u32);
113 };
114
115 return csum;
116}
117
118int spl_check_board_image(struct spl_image_info *spl_image,
119 const struct spl_boot_device *bootdev)
120{
121 u32 csum = *(u32 *)(spl_image->load_addr + spl_image->size - 4);
122
123 if (checksum32((void *)spl_image->load_addr,
124 spl_image->size - 4) != csum) {
125 printf("ERROR: Invalid data checksum in kwbimage\n");
126 return -EINVAL;
127 }
128
129 return 0;
130}
131
Pali Rohárcf97b822021-07-23 11:14:29 +0200132int spl_parse_board_header(struct spl_image_info *spl_image,
Pali Rohárdda8f882022-01-14 14:31:38 +0100133 const struct spl_boot_device *bootdev,
Pali Rohárcf97b822021-07-23 11:14:29 +0200134 const void *image_header, size_t size)
135{
136 const struct kwbimage_main_hdr_v1 *mhdr = image_header;
137
138 if (size < sizeof(*mhdr)) {
139 /* This should be compile time assert */
140 printf("FATAL ERROR: Image header size is too small\n");
141 hang();
142 }
143
144 /*
145 * Very basic check for image validity. We cannot check mhdr->checksum
146 * as it is calculated also from variable length extended headers
147 * (including SPL content) which is not included in U-Boot image_header.
148 */
149 if (mhdr->version != 1 ||
Pali Rohára157e122022-01-14 14:31:39 +0100150 ((mhdr->headersz_msb << 16) | mhdr->headersz_lsb) < sizeof(*mhdr)) {
151 printf("ERROR: Invalid kwbimage v1\n");
152 return -EINVAL;
153 }
154
Marek Behún556eab62022-01-14 14:31:44 +0100155 if (IS_ENABLED(CONFIG_SPL_SPI_FLASH_SUPPORT) &&
156 bootdev->boot_device == BOOT_DEVICE_SPI &&
Pali Rohára157e122022-01-14 14:31:39 +0100157 mhdr->blockid != IBR_HDR_SPI_ID) {
158 printf("ERROR: Wrong blockid (0x%x) in SPI kwbimage\n",
159 mhdr->blockid);
160 return -EINVAL;
161 }
Pali Rohára157e122022-01-14 14:31:39 +0100162
Marek Behún556eab62022-01-14 14:31:44 +0100163 if (IS_ENABLED(CONFIG_SPL_SATA) &&
164 bootdev->boot_device == BOOT_DEVICE_SATA &&
Pali Rohára157e122022-01-14 14:31:39 +0100165 mhdr->blockid != IBR_HDR_SATA_ID) {
166 printf("ERROR: Wrong blockid (0x%x) in SATA kwbimage\n",
167 mhdr->blockid);
168 return -EINVAL;
169 }
Pali Rohára157e122022-01-14 14:31:39 +0100170
Marek Behún556eab62022-01-14 14:31:44 +0100171 if (IS_ENABLED(CONFIG_SPL_MMC) &&
172 (bootdev->boot_device == BOOT_DEVICE_MMC1 ||
Pali Rohára157e122022-01-14 14:31:39 +0100173 bootdev->boot_device == BOOT_DEVICE_MMC2 ||
174 bootdev->boot_device == BOOT_DEVICE_MMC2_2) &&
175 mhdr->blockid != IBR_HDR_SDIO_ID) {
176 printf("ERROR: Wrong blockid (0x%x) in SDIO kwbimage\n",
177 mhdr->blockid);
Pali Rohárcf97b822021-07-23 11:14:29 +0200178 return -EINVAL;
179 }
180
181 spl_image->offset = mhdr->srcaddr;
182
Pali Rohárcf97b822021-07-23 11:14:29 +0200183 /*
184 * For SATA srcaddr is specified in number of sectors.
185 * The main header is must be stored at sector number 1.
186 * This expects that sector size is 512 bytes and recalculates
187 * data offset to bytes relative to the main header.
188 */
Marek Behún556eab62022-01-14 14:31:44 +0100189 if (IS_ENABLED(CONFIG_SPL_SATA) && mhdr->blockid == IBR_HDR_SATA_ID) {
Pali Rohárcf97b822021-07-23 11:14:29 +0200190 if (spl_image->offset < 1) {
Marek Behún46c871a2022-01-14 14:31:42 +0100191 printf("ERROR: Wrong srcaddr (0x%08x) in SATA kwbimage\n",
192 spl_image->offset);
Pali Rohárcf97b822021-07-23 11:14:29 +0200193 return -EINVAL;
194 }
195 spl_image->offset -= 1;
196 spl_image->offset *= 512;
197 }
Pali Rohárcf97b822021-07-23 11:14:29 +0200198
Pali Rohárcf97b822021-07-23 11:14:29 +0200199 /*
200 * For SDIO (eMMC) srcaddr is specified in number of sectors.
201 * This expects that sector size is 512 bytes and recalculates
202 * data offset to bytes.
203 */
Marek Behún556eab62022-01-14 14:31:44 +0100204 if (IS_ENABLED(CONFIG_SPL_MMC) && mhdr->blockid == IBR_HDR_SDIO_ID)
Pali Rohárcf97b822021-07-23 11:14:29 +0200205 spl_image->offset *= 512;
Pali Rohárcf97b822021-07-23 11:14:29 +0200206
Pali Roháreb7e1fc2022-01-14 14:31:37 +0100207 if (spl_image->offset % 4 != 0) {
208 printf("ERROR: Wrong srcaddr (0x%08x) in kwbimage\n",
209 spl_image->offset);
210 return -EINVAL;
211 }
212
213 if (mhdr->blocksize <= 4 || mhdr->blocksize % 4 != 0) {
214 printf("ERROR: Wrong blocksize (0x%08x) in kwbimage\n",
215 mhdr->blocksize);
216 return -EINVAL;
217 }
218
Pali Rohárcf97b822021-07-23 11:14:29 +0200219 spl_image->size = mhdr->blocksize;
220 spl_image->entry_point = mhdr->execaddr;
221 spl_image->load_addr = mhdr->destaddr;
222 spl_image->os = IH_OS_U_BOOT;
223 spl_image->name = "U-Boot";
224
225 return 0;
226}
227
Stefan Roese44e7ebd2016-01-07 14:09:09 +0100228u32 spl_boot_device(void)
229{
Pali Rohárda1be862021-07-23 11:14:26 +0200230 u32 boot_device = get_boot_device();
231
Pali Rohárcf97b822021-07-23 11:14:29 +0200232 switch (boot_device) {
Pali Rohárda1be862021-07-23 11:14:26 +0200233 /*
234 * Return to the BootROM to continue the Marvell xmodem
235 * UART boot protocol. As initiated by the kwboot tool.
236 *
237 * This can only be done by the BootROM since the beginning
238 * of the image is already read and interpreted by the BootROM.
239 * SPL has no chance to receive this information. So we
240 * need to return to the BootROM to enable this xmodem
241 * UART download. Use SPL infrastructure to return to BootROM.
Pali Rohárda1be862021-07-23 11:14:26 +0200242 */
Pali Rohárda1be862021-07-23 11:14:26 +0200243 case BOOT_DEVICE_UART:
Pali Rohárda1be862021-07-23 11:14:26 +0200244 return BOOT_DEVICE_BOOTROM;
Pali Rohárcf97b822021-07-23 11:14:29 +0200245
246 /*
247 * If SPL is compiled with chosen boot_device support
248 * then use SPL driver for loading U-Boot proper.
249 */
Simon Glassb58bfe02021-08-08 12:20:09 -0600250#ifdef CONFIG_SPL_MMC
Pali Rohárcf97b822021-07-23 11:14:29 +0200251 case BOOT_DEVICE_MMC1:
252 return BOOT_DEVICE_MMC1;
253#endif
Simon Glass081a45a2021-08-08 12:20:17 -0600254#ifdef CONFIG_SPL_SATA
Pali Rohár90a88982021-10-29 14:09:48 +0200255 case BOOT_DEVICE_SATA:
256 return BOOT_DEVICE_SATA;
Pali Rohárcf97b822021-07-23 11:14:29 +0200257#endif
258#ifdef CONFIG_SPL_SPI_FLASH_SUPPORT
259 case BOOT_DEVICE_SPI:
260 return BOOT_DEVICE_SPI;
261#endif
262
263 /*
264 * If SPL is not compiled with chosen boot_device support
265 * then return to the BootROM. BootROM supports loading
266 * U-Boot proper from any valid boot_device present in SAR
267 * register.
268 */
Pali Rohárda1be862021-07-23 11:14:26 +0200269 default:
Pali Rohárcf97b822021-07-23 11:14:29 +0200270 return BOOT_DEVICE_BOOTROM;
Pali Rohárda1be862021-07-23 11:14:26 +0200271 }
Stefan Roese63962132015-07-20 11:20:36 +0200272}
273
Marek Behúnee76b4a2021-08-16 15:19:37 +0200274#else
275
276u32 spl_boot_device(void)
277{
278 return BOOT_DEVICE_BOOTROM;
279}
280
281#endif
282
Pali Rohára3a38e52021-07-23 11:14:25 +0200283int board_return_to_bootrom(struct spl_image_info *spl_image,
284 struct spl_boot_device *bootdev)
285{
286 u32 *regs = *(u32 **)CONFIG_SPL_BOOTROM_SAVE;
287
288 printf("Returning to BootROM (return address 0x%08x)...\n", regs[13]);
289 return_to_bootrom();
290
291 /* NOTREACHED - return_to_bootrom() does not return */
292 hang();
293}
294
Stefan Roesee463bf32015-01-19 11:33:42 +0100295void board_init_f(ulong dummy)
296{
Stefan Roese83097cf2015-11-25 07:37:00 +0100297 int ret;
298
Stefan Roesed7f2c122015-04-17 18:13:06 +0200299 /*
300 * Pin muxing needs to be done before UART output, since
301 * on A38x the UART pins need some re-muxing for output
302 * to work.
303 */
304 board_early_init_f();
305
Stefan Roese85bddff2019-04-12 16:42:28 +0200306 /*
307 * Use special translation offset for SPL. This needs to be
308 * configured *before* spl_init() is called as this function
309 * calls dm_init() which calls the bind functions of the
310 * device drivers. Here the base address needs to be configured
311 * (translated) correctly.
312 */
313 gd->translation_offset = 0xd0000000 - 0xf1000000;
314
Stefan Roese83097cf2015-11-25 07:37:00 +0100315 ret = spl_init();
316 if (ret) {
Pali Rohár6e863512021-12-17 18:31:14 +0100317 printf("spl_init() failed: %d\n", ret);
Stefan Roese83097cf2015-11-25 07:37:00 +0100318 hang();
319 }
320
Stefan Roesee463bf32015-01-19 11:33:42 +0100321 preloader_console_init();
322
Stefan Roesed04fe8b2015-07-15 15:36:52 +0200323 timer_init();
324
Stefan Roese479f9af2016-02-10 07:23:00 +0100325 /* Armada 375 does not support SerDes and DDR3 init yet */
326#if !defined(CONFIG_ARMADA_375)
Stefan Roesee463bf32015-01-19 11:33:42 +0100327 /* First init the serdes PHY's */
328 serdes_phy_config();
329
330 /* Setup DDR */
Pali Rohárc87978a2021-08-09 17:44:35 +0200331 ret = ddr3_init();
332 if (ret) {
Pali Rohár6e863512021-12-17 18:31:14 +0100333 printf("ddr3_init() failed: %d\n", ret);
Marek Behún90555af2022-02-17 13:54:42 +0100334 if (IS_ENABLED(CONFIG_DDR_RESET_ON_TRAINING_FAILURE) &&
335 get_boot_device() != BOOT_DEVICE_UART)
336 reset_cpu();
337 else
338 hang();
Pali Rohárc87978a2021-08-09 17:44:35 +0200339 }
Stefan Roese479f9af2016-02-10 07:23:00 +0100340#endif
Stefan Roesee463bf32015-01-19 11:33:42 +0100341
Baruch Siach056e1072019-07-10 18:23:04 +0300342 /* Initialize Auto Voltage Scaling */
343 mv_avs_init();
344
Chris Packham3667bec2020-02-26 19:53:50 +1300345 /* Update read timing control for PCIe */
346 mv_rtc_config();
Stefan Roesee463bf32015-01-19 11:33:42 +0100347}