Tom Rini | 10e4779 | 2018-05-06 17:58:06 -0400 | [diff] [blame] | 1 | // SPDX-License-Identifier: GPL-2.0+ |
Vladimir Zapolskiy | 6b20ef8 | 2012-04-19 04:33:08 +0000 | [diff] [blame] | 2 | /* |
Sylvain Lemieux | eb48e2b | 2015-07-27 13:37:35 -0400 | [diff] [blame] | 3 | * Copyright (C) 2011-2015 by Vladimir Zapolskiy <vz@mleia.com> |
Vladimir Zapolskiy | 6b20ef8 | 2012-04-19 04:33:08 +0000 | [diff] [blame] | 4 | */ |
| 5 | |
| 6 | #include <common.h> |
Simon Glass | 6333448 | 2019-11-14 12:57:39 -0700 | [diff] [blame] | 7 | #include <cpu_func.h> |
Simon Glass | 9758973 | 2020-05-10 11:40:02 -0600 | [diff] [blame] | 8 | #include <init.h> |
Simon Glass | 274e0b0 | 2020-05-10 11:39:56 -0600 | [diff] [blame] | 9 | #include <net.h> |
Albert ARIBAUD \(3ADEV\) | 391e163 | 2015-03-31 11:40:43 +0200 | [diff] [blame] | 10 | #include <netdev.h> |
Vladimir Zapolskiy | 6b20ef8 | 2012-04-19 04:33:08 +0000 | [diff] [blame] | 11 | #include <asm/arch/cpu.h> |
| 12 | #include <asm/arch/clk.h> |
| 13 | #include <asm/arch/wdt.h> |
Albert ARIBAUD \(3ADEV\) | ee69a39 | 2015-03-31 11:40:51 +0200 | [diff] [blame] | 14 | #include <asm/arch/sys_proto.h> |
Vladimir Zapolskiy | 6b20ef8 | 2012-04-19 04:33:08 +0000 | [diff] [blame] | 15 | #include <asm/io.h> |
| 16 | |
| 17 | static struct clk_pm_regs *clk = (struct clk_pm_regs *)CLK_PM_BASE; |
| 18 | static struct wdt_regs *wdt = (struct wdt_regs *)WDT_BASE; |
| 19 | |
Harald Seiler | 6f14d5f | 2020-12-15 16:47:52 +0100 | [diff] [blame] | 20 | void reset_cpu(void) |
Vladimir Zapolskiy | 6b20ef8 | 2012-04-19 04:33:08 +0000 | [diff] [blame] | 21 | { |
| 22 | /* Enable watchdog clock */ |
| 23 | setbits_le32(&clk->timclk_ctrl, CLK_TIMCLK_WATCHDOG); |
| 24 | |
Harald Seiler | 0f57627 | 2020-12-15 16:47:51 +0100 | [diff] [blame] | 25 | /* Reset pulse length is 13005 peripheral clock frames */ |
| 26 | writel(13000, &wdt->pulse); |
Vladimir Zapolskiy | 6b20ef8 | 2012-04-19 04:33:08 +0000 | [diff] [blame] | 27 | |
Harald Seiler | 0f57627 | 2020-12-15 16:47:51 +0100 | [diff] [blame] | 28 | /* Force WDOG_RESET2 and RESOUT_N signal active */ |
| 29 | writel(WDTIM_MCTRL_RESFRC2 | WDTIM_MCTRL_RESFRC1 | WDTIM_MCTRL_M_RES2, |
| 30 | &wdt->mctrl); |
Vladimir Zapolskiy | 6b20ef8 | 2012-04-19 04:33:08 +0000 | [diff] [blame] | 31 | |
| 32 | while (1) |
| 33 | /* NOP */; |
| 34 | } |
| 35 | |
| 36 | #if defined(CONFIG_ARCH_CPU_INIT) |
| 37 | int arch_cpu_init(void) |
| 38 | { |
| 39 | /* |
Bin Meng | 7557405 | 2016-02-05 19:30:11 -0800 | [diff] [blame] | 40 | * It might be necessary to flush data cache, if U-Boot is loaded |
Vladimir Zapolskiy | 6b20ef8 | 2012-04-19 04:33:08 +0000 | [diff] [blame] | 41 | * from kickstart bootloader, e.g. from S1L loader |
| 42 | */ |
| 43 | flush_dcache_all(); |
| 44 | |
| 45 | return 0; |
| 46 | } |
| 47 | #else |
| 48 | #error "You have to select CONFIG_ARCH_CPU_INIT" |
| 49 | #endif |
| 50 | |
| 51 | #if defined(CONFIG_DISPLAY_CPUINFO) |
| 52 | int print_cpuinfo(void) |
| 53 | { |
| 54 | printf("CPU: NXP LPC32XX\n"); |
| 55 | printf("CPU clock: %uMHz\n", get_hclk_pll_rate() / 1000000); |
| 56 | printf("AHB bus clock: %uMHz\n", get_hclk_clk_rate() / 1000000); |
| 57 | printf("Peripheral clock: %uMHz\n", get_periph_clk_rate() / 1000000); |
| 58 | |
| 59 | return 0; |
| 60 | } |
| 61 | #endif |
Albert ARIBAUD \(3ADEV\) | 391e163 | 2015-03-31 11:40:43 +0200 | [diff] [blame] | 62 | |
| 63 | #ifdef CONFIG_LPC32XX_ETH |
Masahiro Yamada | f7ed78b | 2020-06-26 15:13:33 +0900 | [diff] [blame] | 64 | int cpu_eth_init(struct bd_info *bis) |
Albert ARIBAUD \(3ADEV\) | 391e163 | 2015-03-31 11:40:43 +0200 | [diff] [blame] | 65 | { |
| 66 | lpc32xx_eth_initialize(bis); |
| 67 | return 0; |
| 68 | } |
| 69 | #endif |