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Tom Rini53633a82024-02-29 12:33:36 -05001/* SPDX-License-Identifier: GPL-2.0
2 *
3 * Copyright (C) 2018 Renesas Electronics Corp.
4 */
5#ifndef __DT_BINDINGS_CLOCK_R8A77470_CPG_MSSR_H__
6#define __DT_BINDINGS_CLOCK_R8A77470_CPG_MSSR_H__
7
8#include <dt-bindings/clock/renesas-cpg-mssr.h>
9
10/* r8a77470 CPG Core Clocks */
11#define R8A77470_CLK_Z2 0
12#define R8A77470_CLK_ZTR 1
13#define R8A77470_CLK_ZTRD2 2
14#define R8A77470_CLK_ZT 3
15#define R8A77470_CLK_ZX 4
16#define R8A77470_CLK_ZS 5
17#define R8A77470_CLK_HP 6
18#define R8A77470_CLK_B 7
19#define R8A77470_CLK_LB 8
20#define R8A77470_CLK_P 9
21#define R8A77470_CLK_CL 10
22#define R8A77470_CLK_CP 11
23#define R8A77470_CLK_M2 12
24#define R8A77470_CLK_ZB3 13
25#define R8A77470_CLK_SDH 14
26#define R8A77470_CLK_SD0 15
27#define R8A77470_CLK_SD1 16
28#define R8A77470_CLK_SD2 17
29#define R8A77470_CLK_MP 18
30#define R8A77470_CLK_QSPI 19
31#define R8A77470_CLK_CPEX 20
32#define R8A77470_CLK_RCAN 21
33#define R8A77470_CLK_R 22
34#define R8A77470_CLK_OSC 23
35
36#endif /* __DT_BINDINGS_CLOCK_R8A77470_CPG_MSSR_H__ */