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Tom Rini10e47792018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0+
Chunhe Lan8e4f3ff2014-04-14 18:42:06 +08002/*
3 * Copyright 2014 Freescale Semiconductor, Inc.
Chunhe Lan8e4f3ff2014-04-14 18:42:06 +08004 */
5
Tom Rinidec7ea02024-05-20 13:35:03 -06006#include <config.h>
Chunhe Lan8e4f3ff2014-04-14 18:42:06 +08007#include <asm/mmu.h>
Tom Rinidec7ea02024-05-20 13:35:03 -06008#include <asm/ppc.h>
Chunhe Lan8e4f3ff2014-04-14 18:42:06 +08009
10struct fsl_e_tlb_entry tlb_table[] = {
11 /* TLB 0 - for temp stack in cache */
Tom Rini6a5dccc2022-11-16 13:10:41 -050012 SET_TLB_ENTRY(0, CFG_SYS_INIT_RAM_ADDR,
13 CFG_SYS_INIT_RAM_ADDR_PHYS,
Chunhe Lan8e4f3ff2014-04-14 18:42:06 +080014 MAS3_SX|MAS3_SW|MAS3_SR, 0,
15 0, 0, BOOKE_PAGESZ_4K, 0),
Tom Rini6a5dccc2022-11-16 13:10:41 -050016 SET_TLB_ENTRY(0, CFG_SYS_INIT_RAM_ADDR + 4 * 1024,
17 CFG_SYS_INIT_RAM_ADDR_PHYS + 4 * 1024,
Chunhe Lan8e4f3ff2014-04-14 18:42:06 +080018 MAS3_SX|MAS3_SW|MAS3_SR, 0,
19 0, 0, BOOKE_PAGESZ_4K, 0),
Tom Rini6a5dccc2022-11-16 13:10:41 -050020 SET_TLB_ENTRY(0, CFG_SYS_INIT_RAM_ADDR + 8 * 1024,
21 CFG_SYS_INIT_RAM_ADDR_PHYS + 8 * 1024,
Chunhe Lan8e4f3ff2014-04-14 18:42:06 +080022 MAS3_SX|MAS3_SW|MAS3_SR, 0,
23 0, 0, BOOKE_PAGESZ_4K, 0),
Tom Rini6a5dccc2022-11-16 13:10:41 -050024 SET_TLB_ENTRY(0, CFG_SYS_INIT_RAM_ADDR + 12 * 1024,
25 CFG_SYS_INIT_RAM_ADDR_PHYS + 12 * 1024,
Chunhe Lan8e4f3ff2014-04-14 18:42:06 +080026 MAS3_SX|MAS3_SW|MAS3_SR, 0,
27 0, 0, BOOKE_PAGESZ_4K, 0),
28
29 /* TLB 1 */
30 /* *I*** - Covers boot page */
Tom Rini6a5dccc2022-11-16 13:10:41 -050031#if defined(CONFIG_SYS_RAMBOOT) && defined(CFG_SYS_INIT_L3_ADDR)
Chunhe Lan8e4f3ff2014-04-14 18:42:06 +080032 /*
33 * *I*G - L3SRAM. When L3 is used as 512K SRAM */
Tom Rini6a5dccc2022-11-16 13:10:41 -050034 SET_TLB_ENTRY(1, CFG_SYS_INIT_L3_ADDR, CFG_SYS_INIT_L3_ADDR,
Chunhe Lan8e4f3ff2014-04-14 18:42:06 +080035 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
36 0, 0, BOOKE_PAGESZ_512K, 1),
37#else
38 SET_TLB_ENTRY(1, 0xfffff000, 0xfffff000,
39 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
40 0, 0, BOOKE_PAGESZ_4K, 1),
41#endif
42
43 /* *I*G* - CCSRBAR */
Tom Rini6a5dccc2022-11-16 13:10:41 -050044 SET_TLB_ENTRY(1, CFG_SYS_CCSRBAR, CFG_SYS_CCSRBAR_PHYS,
Chunhe Lan8e4f3ff2014-04-14 18:42:06 +080045 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
46 0, 1, BOOKE_PAGESZ_16M, 1),
47
48 /* *I*G* - Flash, localbus */
49 /* This will be changed to *I*G* after relocation to RAM. */
Tom Rini6a5dccc2022-11-16 13:10:41 -050050 SET_TLB_ENTRY(1, CFG_SYS_FLASH_BASE, CFG_SYS_FLASH_BASE_PHYS,
Chunhe Lan8e4f3ff2014-04-14 18:42:06 +080051 MAS3_SX|MAS3_SR, MAS2_W|MAS2_G,
52 0, 2, BOOKE_PAGESZ_256M, 1),
53
Chunhe Lan66cba6b2015-03-20 17:08:54 +080054#ifndef CONFIG_SPL_BUILD
Chunhe Lan8e4f3ff2014-04-14 18:42:06 +080055 /* *I*G* - PCI */
Tom Rini56af6592022-11-16 13:10:33 -050056 SET_TLB_ENTRY(1, CFG_SYS_PCIE1_MEM_VIRT, CFG_SYS_PCIE1_MEM_PHYS,
Chunhe Lan8e4f3ff2014-04-14 18:42:06 +080057 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
58 0, 3, BOOKE_PAGESZ_1G, 1),
59
60 /* *I*G* - PCI */
Tom Rini56af6592022-11-16 13:10:33 -050061 SET_TLB_ENTRY(1, CFG_SYS_PCIE1_MEM_VIRT + 0x40000000,
62 CFG_SYS_PCIE1_MEM_PHYS + 0x40000000,
Chunhe Lan8e4f3ff2014-04-14 18:42:06 +080063 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
64 0, 4, BOOKE_PAGESZ_256M, 1),
65
Tom Rini56af6592022-11-16 13:10:33 -050066 SET_TLB_ENTRY(1, CFG_SYS_PCIE1_MEM_VIRT + 0x50000000,
67 CFG_SYS_PCIE1_MEM_PHYS + 0x50000000,
Chunhe Lan8e4f3ff2014-04-14 18:42:06 +080068 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
69 0, 5, BOOKE_PAGESZ_256M, 1),
70
71 /* *I*G* - PCI I/O */
Tom Rini56af6592022-11-16 13:10:33 -050072 SET_TLB_ENTRY(1, CFG_SYS_PCIE1_IO_VIRT, CFG_SYS_PCIE1_IO_PHYS,
Chunhe Lan8e4f3ff2014-04-14 18:42:06 +080073 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
74 0, 6, BOOKE_PAGESZ_256K, 1),
75
76 /* Bman/Qman */
Tom Rini6a5dccc2022-11-16 13:10:41 -050077#ifdef CFG_SYS_BMAN_MEM_PHYS
78 SET_TLB_ENTRY(1, CFG_SYS_BMAN_MEM_BASE, CFG_SYS_BMAN_MEM_PHYS,
Chunhe Lan8e4f3ff2014-04-14 18:42:06 +080079 MAS3_SX|MAS3_SW|MAS3_SR, 0,
80 0, 9, BOOKE_PAGESZ_16M, 1),
Tom Rini6a5dccc2022-11-16 13:10:41 -050081 SET_TLB_ENTRY(1, CFG_SYS_BMAN_MEM_BASE + 0x01000000,
82 CFG_SYS_BMAN_MEM_PHYS + 0x01000000,
Chunhe Lan8e4f3ff2014-04-14 18:42:06 +080083 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
84 0, 10, BOOKE_PAGESZ_16M, 1),
85#endif
Tom Rini6a5dccc2022-11-16 13:10:41 -050086#ifdef CFG_SYS_QMAN_MEM_PHYS
87 SET_TLB_ENTRY(1, CFG_SYS_QMAN_MEM_BASE, CFG_SYS_QMAN_MEM_PHYS,
Chunhe Lan8e4f3ff2014-04-14 18:42:06 +080088 MAS3_SX|MAS3_SW|MAS3_SR, 0,
89 0, 11, BOOKE_PAGESZ_16M, 1),
Tom Rini6a5dccc2022-11-16 13:10:41 -050090 SET_TLB_ENTRY(1, CFG_SYS_QMAN_MEM_BASE + 0x01000000,
91 CFG_SYS_QMAN_MEM_PHYS + 0x01000000,
Chunhe Lan8e4f3ff2014-04-14 18:42:06 +080092 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
93 0, 12, BOOKE_PAGESZ_16M, 1),
94#endif
Chunhe Lan66cba6b2015-03-20 17:08:54 +080095#endif
96
Tom Rini6a5dccc2022-11-16 13:10:41 -050097#ifdef CFG_SYS_DCSRBAR_PHYS
98 SET_TLB_ENTRY(1, CFG_SYS_DCSRBAR, CFG_SYS_DCSRBAR_PHYS,
Chunhe Lan8e4f3ff2014-04-14 18:42:06 +080099 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
100 0, 13, BOOKE_PAGESZ_32M, 1),
101#endif
Tom Rinib4213492022-11-12 17:36:51 -0500102#ifdef CFG_SYS_NAND_BASE
Chunhe Lan8e4f3ff2014-04-14 18:42:06 +0800103 /*
104 * *I*G - NAND
105 * entry 14 and 15 has been used hard coded, they will be disabled
106 * in cpu_init_f, so we use entry 16 for nand.
107 */
Tom Rinib4213492022-11-12 17:36:51 -0500108 SET_TLB_ENTRY(1, CFG_SYS_NAND_BASE, CFG_SYS_NAND_BASE_PHYS,
Chunhe Lan8e4f3ff2014-04-14 18:42:06 +0800109 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
110 0, 16, BOOKE_PAGESZ_64K, 1),
111#endif
Tom Rini6a5dccc2022-11-16 13:10:41 -0500112#ifdef CFG_SYS_CPLD_BASE
113 SET_TLB_ENTRY(1, CFG_SYS_CPLD_BASE, CFG_SYS_CPLD_BASE_PHYS,
Chunhe Lanc3eb88d2014-09-12 14:47:09 +0800114 MAS3_SW|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
115 0, 17, BOOKE_PAGESZ_4K, 1),
116#endif
Chunhe Lan66cba6b2015-03-20 17:08:54 +0800117#if defined(CONFIG_RAMBOOT_PBL) && !defined(CONFIG_SPL_BUILD)
Tom Rini6a5dccc2022-11-16 13:10:41 -0500118 SET_TLB_ENTRY(1, CFG_SYS_DDR_SDRAM_BASE, CFG_SYS_DDR_SDRAM_BASE,
York Sun05204d02017-12-05 10:57:54 -0800119 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_M,
Chunhe Lan66cba6b2015-03-20 17:08:54 +0800120 0, 18, BOOKE_PAGESZ_2G, 1)
121#endif
Chunhe Lan8e4f3ff2014-04-14 18:42:06 +0800122};
123
124int num_tlb_entries = ARRAY_SIZE(tlb_table);