blob: 5b20accbcb172d7e0e40dc7c92933f5123e1485a [file] [log] [blame]
Michal Simekf5ff7bc2013-06-17 14:37:01 +02001/*
2 * Copyright (C) 2012 - 2013 Michal Simek <monstr@monstr.eu>
3 * Copyright (C) 2012 - 2013 Xilinx, Inc. All rights reserved.
4 *
5 * SPDX-License-Identifier: GPL-2.0+
6 */
7
8#include <common.h>
9#include <asm/io.h>
10#include <asm/arch/sys_proto.h>
11#include <asm/arch/hardware.h>
12
13DECLARE_GLOBAL_DATA_PTR;
14
15/* Control regsiter bitfield definitions */
16#define ZYNQ_DDRC_CTRLREG_BUSWIDTH_MASK 0xC
17#define ZYNQ_DDRC_CTRLREG_BUSWIDTH_SHIFT 2
18#define ZYNQ_DDRC_CTRLREG_BUSWIDTH_16BIT 1
19
20/* ECC scrub regsiter definitions */
21#define ZYNQ_DDRC_ECC_SCRUBREG_ECC_MODE_MASK 0x7
22#define ZYNQ_DDRC_ECC_SCRUBREG_ECCMODE_SECDED 0x4
23
24void zynq_ddrc_init(void)
25{
26 u32 width, ecctype;
27
28 width = readl(&ddrc_base->ddrc_ctrl);
29 width = (width & ZYNQ_DDRC_CTRLREG_BUSWIDTH_MASK) >>
30 ZYNQ_DDRC_CTRLREG_BUSWIDTH_SHIFT;
31 ecctype = (readl(&ddrc_base->ecc_scrub) &
32 ZYNQ_DDRC_ECC_SCRUBREG_ECC_MODE_MASK);
33
34 /* ECC is enabled when memory is in 16bit mode and it is enabled */
35 if ((ecctype == ZYNQ_DDRC_ECC_SCRUBREG_ECCMODE_SECDED) &&
36 (width == ZYNQ_DDRC_CTRLREG_BUSWIDTH_16BIT)) {
Michal Simek79e67942014-05-15 09:40:14 +020037 puts("ECC enabled ");
Michal Simekf5ff7bc2013-06-17 14:37:01 +020038 /*
39 * Clear the first 1MB because it is not initialized from
40 * first stage bootloader. To get ECC to work all memory has
41 * been initialized by writing any value.
42 */
Wolfgang Denk6ae80832014-11-06 14:02:57 +010043 /* cppcheck-suppress nullPointer */
Michal Simek5d688f22014-04-25 14:19:00 +020044 memset((void *)0, 0, 1 * 1024 * 1024);
Michal Simekeb955442013-09-05 08:41:19 +020045
46 gd->ram_size /= 2;
Michal Simekf5ff7bc2013-06-17 14:37:01 +020047 } else {
Michal Simek79e67942014-05-15 09:40:14 +020048 puts("ECC disabled ");
Michal Simekf5ff7bc2013-06-17 14:37:01 +020049 }
Michal Simekf5ff7bc2013-06-17 14:37:01 +020050}