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git01.mediatek.com / filogic / uboot / f1799857207d501f0b832fbebc50750332300fe1 / . / arch / arm / mach-nexell / include / mach / mipi_display.h
blob: f3fdec64647c46582d8f2e9c4f30fecc6568ac1a [file] [log] [blame]
Stefan Bosch48397f12020-07-10 19:07:25 +0200[diff] [blame]1/* SPDX-License-Identifier: GPL-2.0+
2 *
3 * Defines for Mobile Industry Processor Interface (MIPI(R))
4 * Display Working Group standards: DSI, DCS, DBI, DPI
5 *
6 * Copyright (C) 2010 Guennadi Liakhovetski <g.liakhovetski@gmx.de>
7 * Copyright (C) 2006 Nokia Corporation
8 * Author: Imre Deak <imre.deak@nokia.com>
9 */
10
11#ifndef MIPI_DISPLAY_H
12#define MIPI_DISPLAY_H
13
14/* MIPI DSI Processor-to-Peripheral transaction types */
15enum {
16 MIPI_DSI_V_SYNC_START = 0x01,
17 MIPI_DSI_V_SYNC_END = 0x11,
18 MIPI_DSI_H_SYNC_START = 0x21,
19 MIPI_DSI_H_SYNC_END = 0x31,
20
21 MIPI_DSI_COLOR_MODE_OFF = 0x02,
22 MIPI_DSI_COLOR_MODE_ON = 0x12,
23 MIPI_DSI_SHUTDOWN_PERIPHERAL = 0x22,
24 MIPI_DSI_TURN_ON_PERIPHERAL = 0x32,
25
26 MIPI_DSI_GENERIC_SHORT_WRITE_0_PARAM = 0x03,
27 MIPI_DSI_GENERIC_SHORT_WRITE_1_PARAM = 0x13,
28 MIPI_DSI_GENERIC_SHORT_WRITE_2_PARAM = 0x23,
29
30 MIPI_DSI_GENERIC_READ_REQUEST_0_PARAM = 0x04,
31 MIPI_DSI_GENERIC_READ_REQUEST_1_PARAM = 0x14,
32 MIPI_DSI_GENERIC_READ_REQUEST_2_PARAM = 0x24,
33
34 MIPI_DSI_DCS_SHORT_WRITE = 0x05,
35 MIPI_DSI_DCS_SHORT_WRITE_PARAM = 0x15,
36
37 MIPI_DSI_DCS_READ = 0x06,
38
39 MIPI_DSI_SET_MAXIMUM_RETURN_PACKET_SIZE = 0x37,
40
41 MIPI_DSI_END_OF_TRANSMISSION = 0x08,
42
43 MIPI_DSI_NULL_PACKET = 0x09,
44 MIPI_DSI_BLANKING_PACKET = 0x19,
45 MIPI_DSI_GENERIC_LONG_WRITE = 0x29,
46 MIPI_DSI_DCS_LONG_WRITE = 0x39,
47
48 MIPI_DSI_LOOSELY_PACKED_PIXEL_STREAM_YCBCR20 = 0x0c,
49 MIPI_DSI_PACKED_PIXEL_STREAM_YCBCR24 = 0x1c,
50 MIPI_DSI_PACKED_PIXEL_STREAM_YCBCR16 = 0x2c,
51
52 MIPI_DSI_PACKED_PIXEL_STREAM_30 = 0x0d,
53 MIPI_DSI_PACKED_PIXEL_STREAM_36 = 0x1d,
54 MIPI_DSI_PACKED_PIXEL_STREAM_YCBCR12 = 0x3d,
55
56 MIPI_DSI_PACKED_PIXEL_STREAM_16 = 0x0e,
57 MIPI_DSI_PACKED_PIXEL_STREAM_18 = 0x1e,
58 MIPI_DSI_PIXEL_STREAM_3BYTE_18 = 0x2e,
59 MIPI_DSI_PACKED_PIXEL_STREAM_24 = 0x3e,
60};
61
62/* MIPI DSI Peripheral-to-Processor transaction types */
63enum {
64 MIPI_DSI_RX_ACKNOWLEDGE_AND_ERROR_REPORT = 0x02,
65 MIPI_DSI_RX_END_OF_TRANSMISSION = 0x08,
66 MIPI_DSI_RX_GENERIC_SHORT_READ_RESPONSE_1BYTE = 0x11,
67 MIPI_DSI_RX_GENERIC_SHORT_READ_RESPONSE_2BYTE = 0x12,
68 MIPI_DSI_RX_GENERIC_LONG_READ_RESPONSE = 0x1a,
69 MIPI_DSI_RX_DCS_LONG_READ_RESPONSE = 0x1c,
70 MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_1BYTE = 0x21,
71 MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_2BYTE = 0x22,
72};
73
74/* MIPI DCS commands */
75enum {
76 MIPI_DCS_NOP = 0x00,
77 MIPI_DCS_SOFT_RESET = 0x01,
78 MIPI_DCS_GET_DISPLAY_ID = 0x04,
79 MIPI_DCS_GET_RED_CHANNEL = 0x06,
80 MIPI_DCS_GET_GREEN_CHANNEL = 0x07,
81 MIPI_DCS_GET_BLUE_CHANNEL = 0x08,
82 MIPI_DCS_GET_DISPLAY_STATUS = 0x09,
83 MIPI_DCS_GET_POWER_MODE = 0x0A,
84 MIPI_DCS_GET_ADDRESS_MODE = 0x0B,
85 MIPI_DCS_GET_PIXEL_FORMAT = 0x0C,
86 MIPI_DCS_GET_DISPLAY_MODE = 0x0D,
87 MIPI_DCS_GET_SIGNAL_MODE = 0x0E,
88 MIPI_DCS_GET_DIAGNOSTIC_RESULT = 0x0F,
89 MIPI_DCS_ENTER_SLEEP_MODE = 0x10,
90 MIPI_DCS_EXIT_SLEEP_MODE = 0x11,
91 MIPI_DCS_ENTER_PARTIAL_MODE = 0x12,
92 MIPI_DCS_ENTER_NORMAL_MODE = 0x13,
93 MIPI_DCS_EXIT_INVERT_MODE = 0x20,
94 MIPI_DCS_ENTER_INVERT_MODE = 0x21,
95 MIPI_DCS_SET_GAMMA_CURVE = 0x26,
96 MIPI_DCS_SET_DISPLAY_OFF = 0x28,
97 MIPI_DCS_SET_DISPLAY_ON = 0x29,
98 MIPI_DCS_SET_COLUMN_ADDRESS = 0x2A,
99 MIPI_DCS_SET_PAGE_ADDRESS = 0x2B,
100 MIPI_DCS_WRITE_MEMORY_START = 0x2C,
101 MIPI_DCS_WRITE_LUT = 0x2D,
102 MIPI_DCS_READ_MEMORY_START = 0x2E,
103 MIPI_DCS_SET_PARTIAL_AREA = 0x30,
104 MIPI_DCS_SET_SCROLL_AREA = 0x33,
105 MIPI_DCS_SET_TEAR_OFF = 0x34,
106 MIPI_DCS_SET_TEAR_ON = 0x35,
107 MIPI_DCS_SET_ADDRESS_MODE = 0x36,
108 MIPI_DCS_SET_SCROLL_START = 0x37,
109 MIPI_DCS_EXIT_IDLE_MODE = 0x38,
110 MIPI_DCS_ENTER_IDLE_MODE = 0x39,
111 MIPI_DCS_SET_PIXEL_FORMAT = 0x3A,
112 MIPI_DCS_WRITE_MEMORY_CONTINUE = 0x3C,
113 MIPI_DCS_READ_MEMORY_CONTINUE = 0x3E,
114 MIPI_DCS_SET_TEAR_SCANLINE = 0x44,
115 MIPI_DCS_GET_SCANLINE = 0x45,
116 MIPI_DCS_READ_DDB_START = 0xA1,
117 MIPI_DCS_READ_DDB_CONTINUE = 0xA8,
118};
119
120/* MIPI DCS pixel formats */
121#define MIPI_DCS_PIXEL_FMT_24BIT 7
122#define MIPI_DCS_PIXEL_FMT_18BIT 6
123#define MIPI_DCS_PIXEL_FMT_16BIT 5
124#define MIPI_DCS_PIXEL_FMT_12BIT 3
125#define MIPI_DCS_PIXEL_FMT_8BIT 2
126#define MIPI_DCS_PIXEL_FMT_3BIT 1
127
128/* request ACK from peripheral */
129#define MIPI_DSI_MSG_REQ_ACK BIT(0)
130/* use Low Power Mode to transmit message */
131#define MIPI_DSI_MSG_USE_LPM BIT(1)
132
133/**
134 * struct mipi_dsi_msg - read/write DSI buffer
135 * @channel: virtual channel id
136 * @type: payload data type
137 * @flags: flags controlling this message transmission
138 * @tx_len: length of @tx_buf
139 * @tx_buf: data to be written
140 * @rx_len: length of @rx_buf
141 * @rx_buf: data to be read, or NULL
142 */
143struct mipi_dsi_msg {
144 u8 channel; /* virtual channel id */
145 u8 type; /* payload data type */
146 u16 flags; /* flags controlling this message transmission */
147 size_t tx_len;
148 const void *tx_buf;
149 size_t rx_len;
150 void *rx_buf;
151};
152
153/* DSI mode flags */
154
155/* video mode */
156#define MIPI_DSI_MODE_VIDEO BIT(0)
157/* video burst mode */
158#define MIPI_DSI_MODE_VIDEO_BURST BIT(1)
159/* video pulse mode */
160#define MIPI_DSI_MODE_VIDEO_SYNC_PULSE BIT(2)
161/* enable auto vertical count mode */
162#define MIPI_DSI_MODE_VIDEO_AUTO_VERT BIT(3)
163/* enable hsync-end packets in vsync-pulse and v-porch area */
164#define MIPI_DSI_MODE_VIDEO_HSE BIT(4)
165/* disable hfront-porch area */
166#define MIPI_DSI_MODE_VIDEO_HFP BIT(5)
167/* disable hback-porch area */
168#define MIPI_DSI_MODE_VIDEO_HBP BIT(6)
169/* disable hsync-active area */
170#define MIPI_DSI_MODE_VIDEO_HSA BIT(7)
171/* flush display FIFO on vsync pulse */
172#define MIPI_DSI_MODE_VSYNC_FLUSH BIT(8)
173/* disable EoT packets in HS mode */
174#define MIPI_DSI_MODE_EOT_PACKET BIT(9)
175/* device supports non-continuous clock behavior (DSI spec 5.6.1) */
176#define MIPI_DSI_CLOCK_NON_CONTINUOUS BIT(10)
177/* transmit data in low power */
178#define MIPI_DSI_MODE_LPM BIT(11) /* DSI mode flags */
179
180enum mipi_dsi_pixel_format {
181 MIPI_DSI_FMT_RGB888,
182 MIPI_DSI_FMT_RGB666,
183 MIPI_DSI_FMT_RGB666_PACKED,
184 MIPI_DSI_FMT_RGB565,
185};
186
187/**
188 * struct mipi_dsi_device - DSI peripheral device
189 * @host: DSI host for this peripheral
190 * @dev: driver model device node for this peripheral
191 * @channel: virtual channel assigned to the peripheral
192 * @format: pixel format for video mode
193 * @lanes: number of active data lanes
194 * @mode_flags: DSI operation mode related flags
195 */
196struct mipi_dsi_device {
197 unsigned int channel;
198 unsigned int lanes;
199 enum mipi_dsi_pixel_format format;
200 unsigned long mode_flags;
201 struct mipi_panel_ops *ops;
202 ssize_t (*write_buffer)(struct mipi_dsi_device *dsi,
203 const void *data, size_t len);
204};
205
206struct mipi_panel_ops {
207 int (*init)(struct mipi_dsi_device *dsi, int width, int height);
208 int (*prepare)(struct mipi_dsi_device *dsi);
209 int (*unprepare)(struct mipi_dsi_device *dsi);
210 int (*enable)(struct mipi_dsi_device *dsi);
211 int (*disable)(struct mipi_dsi_device *dsi);
212 void *private_data;
213};
214
215#endif