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Paweł Anikiel5ee903d2022-06-17 12:47:20 +02001/* SPDX-License-Identifier: GPL-2.0 */
2/*
3 * Copyright 2022 Google LLC
4 */
5#ifndef __SOCFGPA_CHAMELEONV3_H__
6#define __SOCFGPA_CHAMELEONV3_H__
7
8#include <asm/arch/base_addr_a10.h>
9
Paweł Anikiel5ee903d2022-06-17 12:47:20 +020010/*
11 * U-Boot general configurations
12 */
13
14/* Memory configurations */
15#define PHYS_SDRAM_1_SIZE 0x40000000
16
17/*
18 * Serial / UART configurations
19 */
Tom Rini6a5dccc2022-11-16 13:10:41 -050020#define CFG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600, 115200}
Paweł Anikiel5ee903d2022-06-17 12:47:20 +020021
Tom Rinic9edebe2022-12-04 10:03:50 -050022#define CFG_EXTRA_ENV_SETTINGS \
Paweł Anikiela3382bb2023-02-21 16:17:02 +010023 "distro_bootcmd=bridge enable; " \
24 "load mmc 0:1 ${loadaddr} u-boot.txt; " \
25 "env import -t ${loadaddr}; " \
26 "run bootcmd_txt\0"
Paweł Anikiel5ee903d2022-06-17 12:47:20 +020027
28/*
29 * L4 OSC1 Timer 0
30 */
31/* reload value when timer count to zero */
32#define TIMER_LOAD_VAL 0xFFFFFFFF
33
Paweł Anikiel5ee903d2022-06-17 12:47:20 +020034/* The rest of the configuration is shared */
35#include <configs/socfpga_common.h>
36
37#endif /* __SOCFGPA_CHAMELEONV3_H__ */