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Tom Rini10e47792018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0+
Xiubo Li27e2fe62014-12-16 14:50:33 +08002/*
3 * Copyright 2014 Freescale Semiconductor, Inc.
Biwen Lid15aa9f2019-12-31 15:33:44 +08004 * Copyright 2019 NXP
Xiubo Li27e2fe62014-12-16 14:50:33 +08005 *
6 * FSL DCU Framebuffer driver
Xiubo Li27e2fe62014-12-16 14:50:33 +08007 */
8
Simon Glass3ba929a2020-10-30 21:38:53 -06009#include <asm/global_data.h>
Xiubo Li27e2fe62014-12-16 14:50:33 +080010#include <asm/io.h>
11#include <common.h>
12#include <fsl_dcu_fb.h>
13#include <i2c.h>
Stephen Carlsonf1790922021-06-22 16:38:21 -070014#include "../common/i2c_mux.h"
Xiubo Li27e2fe62014-12-16 14:50:33 +080015#include "div64.h"
16#include "../common/diu_ch7301.h"
17#include "ls1021aqds_qixis.h"
18
19DECLARE_GLOBAL_DATA_PTR;
20
Xiubo Li27e2fe62014-12-16 14:50:33 +080021unsigned int dcu_set_pixel_clock(unsigned int pixclock)
22{
23 unsigned long long div;
24
25 div = (unsigned long long)(gd->bus_clk / 1000);
26 div *= (unsigned long long)pixclock;
27 do_div(div, 1000000000);
28
29 return div;
30}
31
Igor Opaniuk9a0270f2019-06-10 14:47:49 +030032int platform_dcu_init(struct fb_info *fbinfo,
33 unsigned int xres,
34 unsigned int yres,
Xiubo Li27e2fe62014-12-16 14:50:33 +080035 const char *port,
36 struct fb_videomode *dcu_fb_videomode)
37{
38 const char *name;
39 unsigned int pixel_format;
40 int ret;
41 u8 ch;
42
43 /* Mux I2C3+I2C4 as HSYNC+VSYNC */
Igor Opaniukf7c91762021-02-09 13:52:45 +020044#if CONFIG_IS_ENABLED(DM_I2C)
Biwen Lid15aa9f2019-12-31 15:33:44 +080045 struct udevice *dev;
46
47 /* QIXIS device mount on I2C1 bus*/
48 ret = i2c_get_chip_for_busnum(0, CONFIG_SYS_I2C_QIXIS_ADDR,
49 1, &dev);
50 if (ret) {
51 printf("%s: Cannot find udev for a bus %d\n", __func__,
52 0);
53 return ret;
54 }
55 ret = dm_i2c_read(dev, QIXIS_DCU_BRDCFG5, &ch, 1);
56 if (ret) {
57 printf("Error: failed to read I2C @%02x\n",
58 CONFIG_SYS_I2C_QIXIS_ADDR);
59 return ret;
60 }
61 ch &= 0x1F;
62 ch |= 0xA0;
63 ret = dm_i2c_write(dev, QIXIS_DCU_BRDCFG5, &ch, 1);
64
65#else
Xiubo Li27e2fe62014-12-16 14:50:33 +080066 ret = i2c_read(CONFIG_SYS_I2C_QIXIS_ADDR, QIXIS_DCU_BRDCFG5,
67 1, &ch, 1);
68 if (ret) {
69 printf("Error: failed to read I2C @%02x\n",
70 CONFIG_SYS_I2C_QIXIS_ADDR);
71 return ret;
72 }
73 ch &= 0x1F;
74 ch |= 0xA0;
75 ret = i2c_write(CONFIG_SYS_I2C_QIXIS_ADDR, QIXIS_DCU_BRDCFG5,
76 1, &ch, 1);
Biwen Lid15aa9f2019-12-31 15:33:44 +080077#endif
Xiubo Li27e2fe62014-12-16 14:50:33 +080078 if (ret) {
79 printf("Error: failed to write I2C @%02x\n",
80 CONFIG_SYS_I2C_QIXIS_ADDR);
81 return ret;
82 }
83
84 if (strncmp(port, "hdmi", 4) == 0) {
85 unsigned long pixval;
86
87 name = "HDMI";
88
89 pixval = 1000000000 / dcu_fb_videomode->pixclock;
90 pixval *= 1000;
91
Igor Opaniukf7c91762021-02-09 13:52:45 +020092#if !CONFIG_IS_ENABLED(DM_I2C)
Xiubo Li27e2fe62014-12-16 14:50:33 +080093 i2c_set_bus_num(CONFIG_SYS_I2C_DVI_BUS_NUM);
Biwen Lid15aa9f2019-12-31 15:33:44 +080094#endif
95 select_i2c_ch_pca9547(I2C_MUX_CH_CH7301,
96 CONFIG_SYS_I2C_DVI_BUS_NUM);
Xiubo Li27e2fe62014-12-16 14:50:33 +080097 diu_set_dvi_encoder(pixval);
Biwen Lid15aa9f2019-12-31 15:33:44 +080098 select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT,
99 CONFIG_SYS_I2C_DVI_BUS_NUM);
Xiubo Li27e2fe62014-12-16 14:50:33 +0800100 } else {
101 return 0;
102 }
103
104 printf("DCU: Switching to %s monitor @ %ux%u\n", name, xres, yres);
105
106 pixel_format = 32;
Igor Opaniuk9a0270f2019-06-10 14:47:49 +0300107 fsl_dcu_init(fbinfo, xres, yres, pixel_format);
Xiubo Li27e2fe62014-12-16 14:50:33 +0800108
109 return 0;
110}