Joe Hamman | 1bab0b0 | 2007-08-09 15:11:03 -0500 | [diff] [blame] | 1 | /* |
| 2 | * Copyright 2007 Wind River Systems <www.windriver.com> |
| 3 | * Copyright 2007 Embedded Specialties, Inc. |
| 4 | * Joe Hamman <joe.hamman@embeddedspecialties.com> |
| 5 | * |
| 6 | * Copyright 2006 Freescale Semiconductor. |
| 7 | * |
| 8 | * Srikanth Srinivasan (srikanth.srinivasan@freescale.com) |
| 9 | * |
Wolfgang Denk | bd8ec7e | 2013-10-07 13:07:26 +0200 | [diff] [blame] | 10 | * SPDX-License-Identifier: GPL-2.0+ |
Joe Hamman | 1bab0b0 | 2007-08-09 15:11:03 -0500 | [diff] [blame] | 11 | */ |
| 12 | |
| 13 | /* |
| 14 | * SBC8641D board configuration file |
| 15 | * |
| 16 | * Make sure you change the MAC address and other network params first, |
Joe Hershberger | 76f353e | 2015-05-04 14:55:14 -0500 | [diff] [blame] | 17 | * search for CONFIG_SERVERIP, etc in this file. |
Joe Hamman | 1bab0b0 | 2007-08-09 15:11:03 -0500 | [diff] [blame] | 18 | */ |
| 19 | |
| 20 | #ifndef __CONFIG_H |
| 21 | #define __CONFIG_H |
| 22 | |
Paul Gortmaker | 6e66b41 | 2015-10-17 16:40:30 -0400 | [diff] [blame] | 23 | |
Joe Hamman | 1bab0b0 | 2007-08-09 15:11:03 -0500 | [diff] [blame] | 24 | /* High Level Configuration Options */ |
Joe Hamman | 1bab0b0 | 2007-08-09 15:11:03 -0500 | [diff] [blame] | 25 | #define CONFIG_MPC8641 1 /* MPC8641 specific */ |
| 26 | #define CONFIG_SBC8641D 1 /* SBC8641D board specific */ |
Kumar Gala | 56d150e | 2009-03-31 23:02:38 -0500 | [diff] [blame] | 27 | #define CONFIG_MP 1 /* support multiple processors */ |
Joe Hamman | 1bab0b0 | 2007-08-09 15:11:03 -0500 | [diff] [blame] | 28 | #define CONFIG_LINUX_RESET_VEC 0x100 /* Reset vector used by Linux */ |
| 29 | |
Wolfgang Denk | 291ba1b | 2010-10-06 09:05:45 +0200 | [diff] [blame] | 30 | #define CONFIG_SYS_TEXT_BASE 0xfff00000 |
| 31 | |
Joe Hamman | 1bab0b0 | 2007-08-09 15:11:03 -0500 | [diff] [blame] | 32 | #ifdef RUN_DIAG |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 33 | #define CONFIG_SYS_DIAG_ADDR 0xff800000 |
Joe Hamman | 1bab0b0 | 2007-08-09 15:11:03 -0500 | [diff] [blame] | 34 | #endif |
| 35 | |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 36 | #define CONFIG_SYS_RESET_ADDRESS 0xfff00100 |
Joe Hamman | 1bab0b0 | 2007-08-09 15:11:03 -0500 | [diff] [blame] | 37 | |
Becky Bruce | d1cb6cb | 2008-11-03 15:44:01 -0600 | [diff] [blame] | 38 | /* |
| 39 | * virtual address to be used for temporary mappings. There |
| 40 | * should be 128k free at this VA. |
| 41 | */ |
| 42 | #define CONFIG_SYS_SCRATCH_VA 0xe8000000 |
| 43 | |
Kumar Gala | f82666b | 2011-01-04 17:48:51 -0600 | [diff] [blame] | 44 | #define CONFIG_SYS_SRIO |
| 45 | #define CONFIG_SRIO1 /* SRIO port 1 */ |
| 46 | |
Joe Hamman | 18f2f03 | 2007-08-11 06:54:58 -0500 | [diff] [blame] | 47 | #define CONFIG_PCI 1 /* Enable PCIE */ |
Kumar Gala | e78f665 | 2010-07-09 00:02:34 -0500 | [diff] [blame] | 48 | #define CONFIG_PCIE1 1 /* PCIE controler 1 (slot 1) */ |
| 49 | #define CONFIG_PCIE2 1 /* PCIE controler 2 (slot 2) */ |
Joe Hamman | 18f2f03 | 2007-08-11 06:54:58 -0500 | [diff] [blame] | 50 | #define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */ |
Gabor Juhos | b445873 | 2013-05-30 07:06:12 +0000 | [diff] [blame] | 51 | #define CONFIG_PCI_INDIRECT_BRIDGE 1 /* indirect PCI bridge support */ |
Becky Bruce | a756ea7 | 2008-01-23 16:31:03 -0600 | [diff] [blame] | 52 | #define CONFIG_FSL_LAW 1 /* Use common FSL init code */ |
Joe Hamman | 1bab0b0 | 2007-08-09 15:11:03 -0500 | [diff] [blame] | 53 | |
Wolfgang Denk | a1be476 | 2008-05-20 16:00:29 +0200 | [diff] [blame] | 54 | #define CONFIG_TSEC_ENET /* tsec ethernet support */ |
Joe Hamman | 1bab0b0 | 2007-08-09 15:11:03 -0500 | [diff] [blame] | 55 | #define CONFIG_ENV_OVERWRITE |
| 56 | |
Peter Tyser | 86dee4a | 2010-10-07 22:32:48 -0500 | [diff] [blame] | 57 | #define CONFIG_BAT_RW 1 /* Use common BAT rw code */ |
Becky Bruce | 59ddf41 | 2008-08-04 14:01:16 -0500 | [diff] [blame] | 58 | #define CONFIG_HIGH_BATS 1 /* High BATs supported and enabled */ |
| 59 | |
Joe Hamman | 1bab0b0 | 2007-08-09 15:11:03 -0500 | [diff] [blame] | 60 | #undef CONFIG_SPD_EEPROM /* Do not use SPD EEPROM for DDR setup*/ |
Wolfgang Denk | a1be476 | 2008-05-20 16:00:29 +0200 | [diff] [blame] | 61 | #undef CONFIG_DDR_ECC /* only for ECC DDR module */ |
Joe Hamman | 1bab0b0 | 2007-08-09 15:11:03 -0500 | [diff] [blame] | 62 | #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER /* DDR controller or DMA? */ |
| 63 | #define CONFIG_MEM_INIT_VALUE 0xDeadBeef |
| 64 | #define CONFIG_NUM_DDR_CONTROLLERS 2 |
| 65 | #define CACHE_LINE_INTERLEAVING 0x20000000 |
| 66 | #define PAGE_INTERLEAVING 0x21000000 |
| 67 | #define BANK_INTERLEAVING 0x22000000 |
| 68 | #define SUPER_BANK_INTERLEAVING 0x23000000 |
| 69 | |
| 70 | |
| 71 | #define CONFIG_ALTIVEC 1 |
| 72 | |
| 73 | /* |
| 74 | * L2CR setup -- make sure this is right for your board! |
| 75 | */ |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 76 | #define CONFIG_SYS_L2 |
Joe Hamman | 1bab0b0 | 2007-08-09 15:11:03 -0500 | [diff] [blame] | 77 | #define L2_INIT 0 |
| 78 | #define L2_ENABLE (L2CR_L2E) |
| 79 | |
| 80 | #ifndef CONFIG_SYS_CLK_FREQ |
| 81 | #define CONFIG_SYS_CLK_FREQ get_board_sys_clk(0) |
| 82 | #endif |
| 83 | |
| 84 | #define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */ |
| 85 | |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 86 | #undef CONFIG_SYS_DRAM_TEST /* memory test, takes time */ |
| 87 | #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest region */ |
| 88 | #define CONFIG_SYS_MEMTEST_END 0x00400000 |
Joe Hamman | 1bab0b0 | 2007-08-09 15:11:03 -0500 | [diff] [blame] | 89 | |
| 90 | /* |
| 91 | * Base addresses -- Note these are effective addresses where the |
| 92 | * actual resources get mapped (not physical addresses) |
| 93 | */ |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 94 | #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */ |
| 95 | #define CONFIG_SYS_CCSRBAR 0xf8000000 /* relocated CCSRBAR */ |
| 96 | #define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR /* PQII uses CONFIG_SYS_IMMR */ |
Joe Hamman | 1bab0b0 | 2007-08-09 15:11:03 -0500 | [diff] [blame] | 97 | |
Jon Loeliger | ab6960f | 2008-11-20 14:02:56 -0600 | [diff] [blame] | 98 | #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR |
| 99 | #define CONFIG_SYS_CCSRBAR_PHYS_HIGH 0x0 |
Kumar Gala | a37b9ce | 2009-08-05 07:59:35 -0500 | [diff] [blame] | 100 | #define CONFIG_SYS_CCSRBAR_PHYS CONFIG_SYS_CCSRBAR_PHYS_LOW |
Jon Loeliger | ab6960f | 2008-11-20 14:02:56 -0600 | [diff] [blame] | 101 | |
Joe Hamman | 1bab0b0 | 2007-08-09 15:11:03 -0500 | [diff] [blame] | 102 | /* |
| 103 | * DDR Setup |
| 104 | */ |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 105 | #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory */ |
| 106 | #define CONFIG_SYS_DDR_SDRAM_BASE2 0x10000000 /* DDR bank 2 */ |
| 107 | #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE |
| 108 | #define CONFIG_SYS_SDRAM_BASE2 CONFIG_SYS_DDR_SDRAM_BASE2 |
Becky Bruce | d1cb6cb | 2008-11-03 15:44:01 -0600 | [diff] [blame] | 109 | #define CONFIG_SYS_MAX_DDR_BAT_SIZE 0x80000000 /* BAT mapping size */ |
Joe Hamman | 1bab0b0 | 2007-08-09 15:11:03 -0500 | [diff] [blame] | 110 | #define CONFIG_VERY_BIG_RAM |
| 111 | |
Kumar Gala | a7adfe3 | 2008-08-26 15:01:37 -0500 | [diff] [blame] | 112 | #define CONFIG_NUM_DDR_CONTROLLERS 2 |
| 113 | #define CONFIG_DIMM_SLOTS_PER_CTLR 2 |
| 114 | #define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR) |
| 115 | |
Joe Hamman | 1bab0b0 | 2007-08-09 15:11:03 -0500 | [diff] [blame] | 116 | #if defined(CONFIG_SPD_EEPROM) |
| 117 | /* |
| 118 | * Determine DDR configuration from I2C interface. |
| 119 | */ |
| 120 | #define SPD_EEPROM_ADDRESS1 0x51 /* DDR DIMM */ |
| 121 | #define SPD_EEPROM_ADDRESS2 0x52 /* DDR DIMM */ |
| 122 | #define SPD_EEPROM_ADDRESS3 0x53 /* DDR DIMM */ |
| 123 | #define SPD_EEPROM_ADDRESS4 0x54 /* DDR DIMM */ |
| 124 | |
| 125 | #else |
| 126 | /* |
| 127 | * Manually set up DDR1 & DDR2 parameters |
| 128 | */ |
| 129 | |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 130 | #define CONFIG_SYS_SDRAM_SIZE 512 /* DDR is 512MB */ |
Joe Hamman | 1bab0b0 | 2007-08-09 15:11:03 -0500 | [diff] [blame] | 131 | |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 132 | #define CONFIG_SYS_DDR_CS0_BNDS 0x0000000F |
| 133 | #define CONFIG_SYS_DDR_CS1_BNDS 0x00000000 |
| 134 | #define CONFIG_SYS_DDR_CS2_BNDS 0x00000000 |
| 135 | #define CONFIG_SYS_DDR_CS3_BNDS 0x00000000 |
| 136 | #define CONFIG_SYS_DDR_CS0_CONFIG 0x80010102 |
| 137 | #define CONFIG_SYS_DDR_CS1_CONFIG 0x00000000 |
| 138 | #define CONFIG_SYS_DDR_CS2_CONFIG 0x00000000 |
| 139 | #define CONFIG_SYS_DDR_CS3_CONFIG 0x00000000 |
| 140 | #define CONFIG_SYS_DDR_TIMING_3 0x00000000 |
| 141 | #define CONFIG_SYS_DDR_TIMING_0 0x00220802 |
| 142 | #define CONFIG_SYS_DDR_TIMING_1 0x38377322 |
| 143 | #define CONFIG_SYS_DDR_TIMING_2 0x002040c7 |
| 144 | #define CONFIG_SYS_DDR_CFG_1A 0x43008008 |
| 145 | #define CONFIG_SYS_DDR_CFG_2 0x24401000 |
| 146 | #define CONFIG_SYS_DDR_MODE_1 0x23c00542 |
| 147 | #define CONFIG_SYS_DDR_MODE_2 0x00000000 |
| 148 | #define CONFIG_SYS_DDR_MODE_CTL 0x00000000 |
| 149 | #define CONFIG_SYS_DDR_INTERVAL 0x05080100 |
| 150 | #define CONFIG_SYS_DDR_DATA_INIT 0x00000000 |
| 151 | #define CONFIG_SYS_DDR_CLK_CTRL 0x03800000 |
| 152 | #define CONFIG_SYS_DDR_CFG_1B 0xC3008008 |
Joe Hamman | 1bab0b0 | 2007-08-09 15:11:03 -0500 | [diff] [blame] | 153 | |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 154 | #define CONFIG_SYS_DDR2_CS0_BNDS 0x0010001F |
| 155 | #define CONFIG_SYS_DDR2_CS1_BNDS 0x00000000 |
| 156 | #define CONFIG_SYS_DDR2_CS2_BNDS 0x00000000 |
| 157 | #define CONFIG_SYS_DDR2_CS3_BNDS 0x00000000 |
| 158 | #define CONFIG_SYS_DDR2_CS0_CONFIG 0x80010102 |
| 159 | #define CONFIG_SYS_DDR2_CS1_CONFIG 0x00000000 |
| 160 | #define CONFIG_SYS_DDR2_CS2_CONFIG 0x00000000 |
| 161 | #define CONFIG_SYS_DDR2_CS3_CONFIG 0x00000000 |
| 162 | #define CONFIG_SYS_DDR2_EXT_REFRESH 0x00000000 |
| 163 | #define CONFIG_SYS_DDR2_TIMING_0 0x00220802 |
| 164 | #define CONFIG_SYS_DDR2_TIMING_1 0x38377322 |
| 165 | #define CONFIG_SYS_DDR2_TIMING_2 0x002040c7 |
| 166 | #define CONFIG_SYS_DDR2_CFG_1A 0x43008008 |
| 167 | #define CONFIG_SYS_DDR2_CFG_2 0x24401000 |
| 168 | #define CONFIG_SYS_DDR2_MODE_1 0x23c00542 |
| 169 | #define CONFIG_SYS_DDR2_MODE_2 0x00000000 |
| 170 | #define CONFIG_SYS_DDR2_MODE_CTL 0x00000000 |
| 171 | #define CONFIG_SYS_DDR2_INTERVAL 0x05080100 |
| 172 | #define CONFIG_SYS_DDR2_DATA_INIT 0x00000000 |
| 173 | #define CONFIG_SYS_DDR2_CLK_CTRL 0x03800000 |
| 174 | #define CONFIG_SYS_DDR2_CFG_1B 0xC3008008 |
Joe Hamman | 1bab0b0 | 2007-08-09 15:11:03 -0500 | [diff] [blame] | 175 | |
| 176 | |
| 177 | #endif |
| 178 | |
Jean-Christophe PLAGNIOL-VILLARD | 8349c72 | 2008-08-30 23:54:58 +0200 | [diff] [blame] | 179 | /* #define CONFIG_ID_EEPROM 1 |
Joe Hamman | 1bab0b0 | 2007-08-09 15:11:03 -0500 | [diff] [blame] | 180 | #define ID_EEPROM_ADDR 0x57 */ |
| 181 | |
| 182 | /* |
| 183 | * The SBC8641D contains 16MB flash space at ff000000. |
| 184 | */ |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 185 | #define CONFIG_SYS_FLASH_BASE 0xff000000 /* start of FLASH 16M */ |
Joe Hamman | 1bab0b0 | 2007-08-09 15:11:03 -0500 | [diff] [blame] | 186 | |
| 187 | /* Flash */ |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 188 | #define CONFIG_SYS_BR0_PRELIM 0xff001001 /* port size 16bit */ |
| 189 | #define CONFIG_SYS_OR0_PRELIM 0xff006e65 /* 16MB Boot Flash area */ |
Joe Hamman | 1bab0b0 | 2007-08-09 15:11:03 -0500 | [diff] [blame] | 190 | |
| 191 | /* 64KB EEPROM */ |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 192 | #define CONFIG_SYS_BR1_PRELIM 0xf0000801 /* port size 16bit */ |
| 193 | #define CONFIG_SYS_OR1_PRELIM 0xffff6e65 /* 64K EEPROM area */ |
Joe Hamman | 1bab0b0 | 2007-08-09 15:11:03 -0500 | [diff] [blame] | 194 | |
| 195 | /* EPLD - User switches, board id, LEDs */ |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 196 | #define CONFIG_SYS_BR2_PRELIM 0xf1000801 /* port size 16bit */ |
| 197 | #define CONFIG_SYS_OR2_PRELIM 0xfff06e65 /* EPLD (switches, board ID, LEDs) area */ |
Joe Hamman | 1bab0b0 | 2007-08-09 15:11:03 -0500 | [diff] [blame] | 198 | |
| 199 | /* Local bus SDRAM 128MB */ |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 200 | #define CONFIG_SYS_BR3_PRELIM 0xe0001861 /* port size ?bit */ |
| 201 | #define CONFIG_SYS_OR3_PRELIM 0xfc006cc0 /* 128MB local bus SDRAM area (1st half) */ |
| 202 | #define CONFIG_SYS_BR4_PRELIM 0xe4001861 /* port size ?bit */ |
| 203 | #define CONFIG_SYS_OR4_PRELIM 0xfc006cc0 /* 128MB local bus SDRAM area (2nd half) */ |
Joe Hamman | 1bab0b0 | 2007-08-09 15:11:03 -0500 | [diff] [blame] | 204 | |
| 205 | /* Disk on Chip (DOC) 128MB */ |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 206 | #define CONFIG_SYS_BR5_PRELIM 0xe8001001 /* port size ?bit */ |
| 207 | #define CONFIG_SYS_OR5_PRELIM 0xf8006e65 /* 128MB local bus SDRAM area (2nd half) */ |
Joe Hamman | 1bab0b0 | 2007-08-09 15:11:03 -0500 | [diff] [blame] | 208 | |
| 209 | /* LCD */ |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 210 | #define CONFIG_SYS_BR6_PRELIM 0xf4000801 /* port size ?bit */ |
| 211 | #define CONFIG_SYS_OR6_PRELIM 0xfff06e65 /* 128MB local bus SDRAM area (2nd half) */ |
Joe Hamman | 1bab0b0 | 2007-08-09 15:11:03 -0500 | [diff] [blame] | 212 | |
| 213 | /* Control logic & misc peripherals */ |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 214 | #define CONFIG_SYS_BR7_PRELIM 0xf2000801 /* port size ?bit */ |
| 215 | #define CONFIG_SYS_OR7_PRELIM 0xfff06e65 /* 128MB local bus SDRAM area (2nd half) */ |
Joe Hamman | 1bab0b0 | 2007-08-09 15:11:03 -0500 | [diff] [blame] | 216 | |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 217 | #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ |
| 218 | #define CONFIG_SYS_MAX_FLASH_SECT 131 /* sectors per device */ |
Joe Hamman | 1bab0b0 | 2007-08-09 15:11:03 -0500 | [diff] [blame] | 219 | |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 220 | #undef CONFIG_SYS_FLASH_CHECKSUM |
| 221 | #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ |
| 222 | #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ |
Wolfgang Denk | 0708bc6 | 2010-10-07 21:51:12 +0200 | [diff] [blame] | 223 | #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ |
Becky Bruce | 2a97867 | 2008-11-05 14:55:35 -0600 | [diff] [blame] | 224 | #define CONFIG_SYS_MONITOR_BASE_EARLY 0xfff00000 /* early monitor loc */ |
Joe Hamman | 1bab0b0 | 2007-08-09 15:11:03 -0500 | [diff] [blame] | 225 | |
Jean-Christophe PLAGNIOL-VILLARD | 8d94c23 | 2008-08-13 01:40:42 +0200 | [diff] [blame] | 226 | #define CONFIG_FLASH_CFI_DRIVER |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 227 | #define CONFIG_SYS_FLASH_CFI |
| 228 | #define CONFIG_SYS_WRITE_SWAPPED_DATA |
| 229 | #define CONFIG_SYS_FLASH_EMPTY_INFO |
| 230 | #define CONFIG_SYS_FLASH_PROTECTION |
Joe Hamman | 1bab0b0 | 2007-08-09 15:11:03 -0500 | [diff] [blame] | 231 | |
| 232 | #undef CONFIG_CLOCKS_IN_MHZ |
| 233 | |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 234 | #define CONFIG_SYS_INIT_RAM_LOCK 1 |
| 235 | #ifndef CONFIG_SYS_INIT_RAM_LOCK |
| 236 | #define CONFIG_SYS_INIT_RAM_ADDR 0x0fd00000 /* Initial RAM address */ |
Joe Hamman | 1bab0b0 | 2007-08-09 15:11:03 -0500 | [diff] [blame] | 237 | #else |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 238 | #define CONFIG_SYS_INIT_RAM_ADDR 0xf8400000 /* Initial RAM address */ |
Joe Hamman | 1bab0b0 | 2007-08-09 15:11:03 -0500 | [diff] [blame] | 239 | #endif |
Wolfgang Denk | 1c2e98e | 2010-10-26 13:32:32 +0200 | [diff] [blame] | 240 | #define CONFIG_SYS_INIT_RAM_SIZE 0x4000 /* Size of used area in RAM */ |
Joe Hamman | 1bab0b0 | 2007-08-09 15:11:03 -0500 | [diff] [blame] | 241 | |
Wolfgang Denk | 0191e47 | 2010-10-26 14:34:52 +0200 | [diff] [blame] | 242 | #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 243 | #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET |
Joe Hamman | 1bab0b0 | 2007-08-09 15:11:03 -0500 | [diff] [blame] | 244 | |
Paul Gortmaker | 7095ab3 | 2015-10-17 16:40:31 -0400 | [diff] [blame] | 245 | #define CONFIG_SYS_MONITOR_LEN (384 * 1024) /* Reserve 384 kB for Mon */ |
Paul Gortmaker | efdcea5 | 2015-10-17 16:40:27 -0400 | [diff] [blame] | 246 | #define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc */ |
Joe Hamman | 1bab0b0 | 2007-08-09 15:11:03 -0500 | [diff] [blame] | 247 | |
| 248 | /* Serial Port */ |
| 249 | #define CONFIG_CONS_INDEX 1 |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 250 | #define CONFIG_SYS_NS16550_SERIAL |
| 251 | #define CONFIG_SYS_NS16550_REG_SIZE 1 |
| 252 | #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) |
Joe Hamman | 1bab0b0 | 2007-08-09 15:11:03 -0500 | [diff] [blame] | 253 | |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 254 | #define CONFIG_SYS_BAUDRATE_TABLE \ |
Joe Hamman | 1bab0b0 | 2007-08-09 15:11:03 -0500 | [diff] [blame] | 255 | {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200} |
| 256 | |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 257 | #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500) |
| 258 | #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600) |
Joe Hamman | 1bab0b0 | 2007-08-09 15:11:03 -0500 | [diff] [blame] | 259 | |
| 260 | /* Use the HUSH parser */ |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 261 | #define CONFIG_SYS_HUSH_PARSER |
| 262 | #ifdef CONFIG_SYS_HUSH_PARSER |
Joe Hamman | 1bab0b0 | 2007-08-09 15:11:03 -0500 | [diff] [blame] | 263 | #endif |
| 264 | |
| 265 | /* |
Joe Hamman | 1bab0b0 | 2007-08-09 15:11:03 -0500 | [diff] [blame] | 266 | * I2C |
| 267 | */ |
Heiko Schocher | f285074 | 2012-10-24 13:48:22 +0200 | [diff] [blame] | 268 | #define CONFIG_SYS_I2C |
| 269 | #define CONFIG_SYS_I2C_FSL |
| 270 | #define CONFIG_SYS_FSL_I2C_SPEED 400000 |
| 271 | #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F |
| 272 | #define CONFIG_SYS_FSL_I2C_OFFSET 0x3100 |
| 273 | #define CONFIG_SYS_I2C_NOPROBES { {0, 0x69} } |
Joe Hamman | 1bab0b0 | 2007-08-09 15:11:03 -0500 | [diff] [blame] | 274 | |
| 275 | /* |
| 276 | * RapidIO MMU |
| 277 | */ |
Kumar Gala | f82666b | 2011-01-04 17:48:51 -0600 | [diff] [blame] | 278 | #define CONFIG_SYS_SRIO1_MEM_BASE 0xc0000000 /* base address */ |
| 279 | #define CONFIG_SYS_SRIO1_MEM_PHYS CONFIG_SYS_SRIO1_MEM_BASE |
| 280 | #define CONFIG_SYS_SRIO1_MEM_SIZE 0x20000000 /* 128M */ |
Joe Hamman | 1bab0b0 | 2007-08-09 15:11:03 -0500 | [diff] [blame] | 281 | |
| 282 | /* |
| 283 | * General PCI |
| 284 | * Addresses are mapped 1-1. |
| 285 | */ |
Kumar Gala | e78f665 | 2010-07-09 00:02:34 -0500 | [diff] [blame] | 286 | #define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000 |
| 287 | #define CONFIG_SYS_PCIE1_MEM_PHYS CONFIG_SYS_PCIE1_MEM_BUS |
| 288 | #define CONFIG_SYS_PCIE1_MEM_VIRT CONFIG_SYS_PCIE1_MEM_BUS |
| 289 | #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ |
| 290 | #define CONFIG_SYS_PCIE1_IO_BUS 0xe2000000 |
| 291 | #define CONFIG_SYS_PCIE1_IO_PHYS CONFIG_SYS_PCIE1_IO_BUS |
| 292 | #define CONFIG_SYS_PCIE1_IO_VIRT CONFIG_SYS_PCIE1_IO_BUS |
| 293 | #define CONFIG_SYS_PCIE1_IO_SIZE 0x1000000 /* 16M */ |
Joe Hamman | 1bab0b0 | 2007-08-09 15:11:03 -0500 | [diff] [blame] | 294 | |
Kumar Gala | e78f665 | 2010-07-09 00:02:34 -0500 | [diff] [blame] | 295 | #define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000 |
| 296 | #define CONFIG_SYS_PCIE2_MEM_PHYS CONFIG_SYS_PCIE2_MEM_BUS |
| 297 | #define CONFIG_SYS_PCIE2_MEM_VIRT CONFIG_SYS_PCIE2_MEM_BUS |
| 298 | #define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000 /* 256M */ |
| 299 | #define CONFIG_SYS_PCIE2_IO_BUS 0xe3000000 |
| 300 | #define CONFIG_SYS_PCIE2_IO_PHYS CONFIG_SYS_PCIE2_IO_BUS |
| 301 | #define CONFIG_SYS_PCIE2_IO_VIRT CONFIG_SYS_PCIE2_IO_BUS |
| 302 | #define CONFIG_SYS_PCIE2_IO_SIZE 0x1000000 /* 16M */ |
Joe Hamman | 1bab0b0 | 2007-08-09 15:11:03 -0500 | [diff] [blame] | 303 | |
| 304 | #if defined(CONFIG_PCI) |
| 305 | |
| 306 | #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ |
| 307 | |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 308 | #undef CONFIG_SYS_SCSI_SCAN_BUS_REVERSE |
Joe Hamman | 1bab0b0 | 2007-08-09 15:11:03 -0500 | [diff] [blame] | 309 | |
Wolfgang Denk | a1be476 | 2008-05-20 16:00:29 +0200 | [diff] [blame] | 310 | #define CONFIG_PCI_PNP /* do pci plug-and-play */ |
Joe Hamman | 1bab0b0 | 2007-08-09 15:11:03 -0500 | [diff] [blame] | 311 | |
| 312 | #undef CONFIG_EEPRO100 |
| 313 | #undef CONFIG_TULIP |
| 314 | |
| 315 | #if !defined(CONFIG_PCI_PNP) |
| 316 | #define PCI_ENET0_IOADDR 0xe0000000 |
| 317 | #define PCI_ENET0_MEMADDR 0xe0000000 |
Wolfgang Denk | a1be476 | 2008-05-20 16:00:29 +0200 | [diff] [blame] | 318 | #define PCI_IDSEL_NUMBER 0x0c /* slot0->3(IDSEL)=12->15 */ |
Joe Hamman | 1bab0b0 | 2007-08-09 15:11:03 -0500 | [diff] [blame] | 319 | #endif |
| 320 | |
| 321 | #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ |
| 322 | |
| 323 | #define CONFIG_DOS_PARTITION |
| 324 | #undef CONFIG_SCSI_AHCI |
| 325 | |
| 326 | #ifdef CONFIG_SCSI_AHCI |
| 327 | #define CONFIG_SATA_ULI5288 |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 328 | #define CONFIG_SYS_SCSI_MAX_SCSI_ID 4 |
| 329 | #define CONFIG_SYS_SCSI_MAX_LUN 1 |
| 330 | #define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * CONFIG_SYS_SCSI_MAX_LUN) |
| 331 | #define CONFIG_SYS_SCSI_MAXDEVICE CONFIG_SYS_SCSI_MAX_DEVICE |
Joe Hamman | 1bab0b0 | 2007-08-09 15:11:03 -0500 | [diff] [blame] | 332 | #endif |
| 333 | |
| 334 | #endif /* CONFIG_PCI */ |
| 335 | |
| 336 | #if defined(CONFIG_TSEC_ENET) |
| 337 | |
Joe Hamman | 1bab0b0 | 2007-08-09 15:11:03 -0500 | [diff] [blame] | 338 | /* #define CONFIG_MII 1 */ /* MII PHY management */ |
| 339 | |
| 340 | #define CONFIG_TSEC1 1 |
| 341 | #define CONFIG_TSEC1_NAME "eTSEC1" |
| 342 | #define CONFIG_TSEC2 1 |
| 343 | #define CONFIG_TSEC2_NAME "eTSEC2" |
| 344 | #define CONFIG_TSEC3 1 |
| 345 | #define CONFIG_TSEC3_NAME "eTSEC3" |
| 346 | #define CONFIG_TSEC4 1 |
| 347 | #define CONFIG_TSEC4_NAME "eTSEC4" |
| 348 | |
| 349 | #define TSEC1_PHY_ADDR 0x1F |
| 350 | #define TSEC2_PHY_ADDR 0x00 |
| 351 | #define TSEC3_PHY_ADDR 0x01 |
| 352 | #define TSEC4_PHY_ADDR 0x02 |
| 353 | #define TSEC1_PHYIDX 0 |
| 354 | #define TSEC2_PHYIDX 0 |
| 355 | #define TSEC3_PHYIDX 0 |
| 356 | #define TSEC4_PHYIDX 0 |
Andy Fleming | 09b88df | 2007-08-15 20:03:25 -0500 | [diff] [blame] | 357 | #define TSEC1_FLAGS TSEC_GIGABIT |
| 358 | #define TSEC2_FLAGS TSEC_GIGABIT |
| 359 | #define TSEC3_FLAGS TSEC_GIGABIT |
| 360 | #define TSEC4_FLAGS TSEC_GIGABIT |
Joe Hamman | 1bab0b0 | 2007-08-09 15:11:03 -0500 | [diff] [blame] | 361 | |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 362 | #define CONFIG_SYS_TBIPA_VALUE 0x1e /* Set TBI address not to conflict with TSEC1_PHY_ADDR */ |
Joe Hamman | 1bab0b0 | 2007-08-09 15:11:03 -0500 | [diff] [blame] | 363 | |
| 364 | #define CONFIG_ETHPRIME "eTSEC1" |
| 365 | |
| 366 | #endif /* CONFIG_TSEC_ENET */ |
| 367 | |
| 368 | /* |
| 369 | * BAT0 2G Cacheable, non-guarded |
| 370 | * 0x0000_0000 2G DDR |
| 371 | */ |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 372 | #define CONFIG_SYS_DBAT0L (BATL_PP_RW | BATL_MEMCOHERENCE) |
| 373 | #define CONFIG_SYS_DBAT0U (BATU_BL_2G | BATU_VS | BATU_VP) |
| 374 | #define CONFIG_SYS_IBAT0L (BATL_PP_RW | BATL_MEMCOHERENCE ) |
| 375 | #define CONFIG_SYS_IBAT0U CONFIG_SYS_DBAT0U |
Joe Hamman | 1bab0b0 | 2007-08-09 15:11:03 -0500 | [diff] [blame] | 376 | |
| 377 | /* |
| 378 | * BAT1 1G Cache-inhibited, guarded |
| 379 | * 0x8000_0000 512M PCI-Express 1 Memory |
| 380 | * 0xa000_0000 512M PCI-Express 2 Memory |
| 381 | * Changed it for operating from 0xd0000000 |
| 382 | */ |
Kumar Gala | e78f665 | 2010-07-09 00:02:34 -0500 | [diff] [blame] | 383 | #define CONFIG_SYS_DBAT1L ( CONFIG_SYS_PCIE1_MEM_PHYS | BATL_PP_RW \ |
Joe Hamman | 1bab0b0 | 2007-08-09 15:11:03 -0500 | [diff] [blame] | 384 | | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) |
Kumar Gala | e78f665 | 2010-07-09 00:02:34 -0500 | [diff] [blame] | 385 | #define CONFIG_SYS_DBAT1U (CONFIG_SYS_PCIE1_MEM_VIRT | BATU_BL_256M | BATU_VS | BATU_VP) |
| 386 | #define CONFIG_SYS_IBAT1L (CONFIG_SYS_PCIE1_MEM_PHYS | BATL_PP_RW | BATL_CACHEINHIBIT) |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 387 | #define CONFIG_SYS_IBAT1U CONFIG_SYS_DBAT1U |
Joe Hamman | 1bab0b0 | 2007-08-09 15:11:03 -0500 | [diff] [blame] | 388 | |
| 389 | /* |
| 390 | * BAT2 512M Cache-inhibited, guarded |
| 391 | * 0xc000_0000 512M RapidIO Memory |
| 392 | */ |
Kumar Gala | f82666b | 2011-01-04 17:48:51 -0600 | [diff] [blame] | 393 | #define CONFIG_SYS_DBAT2L (CONFIG_SYS_SRIO1_MEM_BASE | BATL_PP_RW \ |
Joe Hamman | 1bab0b0 | 2007-08-09 15:11:03 -0500 | [diff] [blame] | 394 | | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) |
Kumar Gala | f82666b | 2011-01-04 17:48:51 -0600 | [diff] [blame] | 395 | #define CONFIG_SYS_DBAT2U (CONFIG_SYS_SRIO1_MEM_BASE | BATU_BL_512M | BATU_VS | BATU_VP) |
| 396 | #define CONFIG_SYS_IBAT2L (CONFIG_SYS_SRIO1_MEM_BASE | BATL_PP_RW | BATL_CACHEINHIBIT) |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 397 | #define CONFIG_SYS_IBAT2U CONFIG_SYS_DBAT2U |
Joe Hamman | 1bab0b0 | 2007-08-09 15:11:03 -0500 | [diff] [blame] | 398 | |
| 399 | /* |
| 400 | * BAT3 4M Cache-inhibited, guarded |
| 401 | * 0xf800_0000 4M CCSR |
| 402 | */ |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 403 | #define CONFIG_SYS_DBAT3L ( CONFIG_SYS_CCSRBAR | BATL_PP_RW \ |
Joe Hamman | 1bab0b0 | 2007-08-09 15:11:03 -0500 | [diff] [blame] | 404 | | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 405 | #define CONFIG_SYS_DBAT3U (CONFIG_SYS_CCSRBAR | BATU_BL_4M | BATU_VS | BATU_VP) |
| 406 | #define CONFIG_SYS_IBAT3L (CONFIG_SYS_CCSRBAR | BATL_PP_RW | BATL_CACHEINHIBIT) |
| 407 | #define CONFIG_SYS_IBAT3U CONFIG_SYS_DBAT3U |
Joe Hamman | 1bab0b0 | 2007-08-09 15:11:03 -0500 | [diff] [blame] | 408 | |
Jon Loeliger | ab6960f | 2008-11-20 14:02:56 -0600 | [diff] [blame] | 409 | #if (CONFIG_SYS_CCSRBAR_DEFAULT != CONFIG_SYS_CCSRBAR) |
| 410 | #define CONFIG_SYS_CCSR_DEFAULT_DBATL (CONFIG_SYS_CCSRBAR_DEFAULT \ |
| 411 | | BATL_PP_RW | BATL_CACHEINHIBIT \ |
| 412 | | BATL_GUARDEDSTORAGE) |
| 413 | #define CONFIG_SYS_CCSR_DEFAULT_DBATU (CONFIG_SYS_CCSRBAR_DEFAULT \ |
| 414 | | BATU_BL_1M | BATU_VS | BATU_VP) |
| 415 | #define CONFIG_SYS_CCSR_DEFAULT_IBATL (CONFIG_SYS_CCSRBAR_DEFAULT \ |
| 416 | | BATL_PP_RW | BATL_CACHEINHIBIT) |
| 417 | #define CONFIG_SYS_CCSR_DEFAULT_IBATU CONFIG_SYS_CCSR_DEFAULT_DBATU |
| 418 | #endif |
| 419 | |
Joe Hamman | 1bab0b0 | 2007-08-09 15:11:03 -0500 | [diff] [blame] | 420 | /* |
| 421 | * BAT4 32M Cache-inhibited, guarded |
| 422 | * 0xe200_0000 16M PCI-Express 1 I/O |
| 423 | * 0xe300_0000 16M PCI-Express 2 I/0 |
| 424 | * Note that this is at 0xe0000000 |
| 425 | */ |
Kumar Gala | e78f665 | 2010-07-09 00:02:34 -0500 | [diff] [blame] | 426 | #define CONFIG_SYS_DBAT4L ( CONFIG_SYS_PCIE1_IO_PHYS | BATL_PP_RW \ |
Joe Hamman | 1bab0b0 | 2007-08-09 15:11:03 -0500 | [diff] [blame] | 427 | | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) |
Kumar Gala | e78f665 | 2010-07-09 00:02:34 -0500 | [diff] [blame] | 428 | #define CONFIG_SYS_DBAT4U (CONFIG_SYS_PCIE1_IO_VIRT | BATU_BL_32M | BATU_VS | BATU_VP) |
| 429 | #define CONFIG_SYS_IBAT4L (CONFIG_SYS_PCIE1_IO_PHYS | BATL_PP_RW | BATL_CACHEINHIBIT) |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 430 | #define CONFIG_SYS_IBAT4U CONFIG_SYS_DBAT4U |
Joe Hamman | 1bab0b0 | 2007-08-09 15:11:03 -0500 | [diff] [blame] | 431 | |
| 432 | /* |
| 433 | * BAT5 128K Cacheable, non-guarded |
| 434 | * 0xe401_0000 128K Init RAM for stack in the CPU DCache (no backing memory) |
| 435 | */ |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 436 | #define CONFIG_SYS_DBAT5L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW | BATL_MEMCOHERENCE) |
| 437 | #define CONFIG_SYS_DBAT5U (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP) |
| 438 | #define CONFIG_SYS_IBAT5L CONFIG_SYS_DBAT5L |
| 439 | #define CONFIG_SYS_IBAT5U CONFIG_SYS_DBAT5U |
Joe Hamman | 1bab0b0 | 2007-08-09 15:11:03 -0500 | [diff] [blame] | 440 | |
| 441 | /* |
| 442 | * BAT6 32M Cache-inhibited, guarded |
| 443 | * 0xfe00_0000 32M FLASH |
| 444 | */ |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 445 | #define CONFIG_SYS_DBAT6L ((CONFIG_SYS_FLASH_BASE & 0xfe000000) | BATL_PP_RW \ |
Joe Hamman | 1bab0b0 | 2007-08-09 15:11:03 -0500 | [diff] [blame] | 446 | | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 447 | #define CONFIG_SYS_DBAT6U ((CONFIG_SYS_FLASH_BASE & 0xfe000000) | BATU_BL_32M | BATU_VS | BATU_VP) |
| 448 | #define CONFIG_SYS_IBAT6L ((CONFIG_SYS_FLASH_BASE & 0xfe000000) | BATL_PP_RW | BATL_MEMCOHERENCE) |
| 449 | #define CONFIG_SYS_IBAT6U CONFIG_SYS_DBAT6U |
Joe Hamman | 1bab0b0 | 2007-08-09 15:11:03 -0500 | [diff] [blame] | 450 | |
Becky Bruce | 2a97867 | 2008-11-05 14:55:35 -0600 | [diff] [blame] | 451 | /* Map the last 1M of flash where we're running from reset */ |
| 452 | #define CONFIG_SYS_DBAT6L_EARLY (CONFIG_SYS_MONITOR_BASE_EARLY | BATL_PP_RW \ |
| 453 | | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) |
Wolfgang Denk | 0708bc6 | 2010-10-07 21:51:12 +0200 | [diff] [blame] | 454 | #define CONFIG_SYS_DBAT6U_EARLY (CONFIG_SYS_TEXT_BASE | BATU_BL_1M | BATU_VS | BATU_VP) |
Becky Bruce | 2a97867 | 2008-11-05 14:55:35 -0600 | [diff] [blame] | 455 | #define CONFIG_SYS_IBAT6L_EARLY (CONFIG_SYS_MONITOR_BASE_EARLY | BATL_PP_RW \ |
| 456 | | BATL_MEMCOHERENCE) |
| 457 | #define CONFIG_SYS_IBAT6U_EARLY CONFIG_SYS_DBAT6U_EARLY |
| 458 | |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 459 | #define CONFIG_SYS_DBAT7L 0x00000000 |
| 460 | #define CONFIG_SYS_DBAT7U 0x00000000 |
| 461 | #define CONFIG_SYS_IBAT7L 0x00000000 |
| 462 | #define CONFIG_SYS_IBAT7U 0x00000000 |
Joe Hamman | 1bab0b0 | 2007-08-09 15:11:03 -0500 | [diff] [blame] | 463 | |
| 464 | /* |
| 465 | * Environment |
| 466 | */ |
Jean-Christophe PLAGNIOL-VILLARD | 53db4cd | 2008-09-10 22:48:04 +0200 | [diff] [blame] | 467 | #define CONFIG_ENV_IS_IN_FLASH 1 |
Paul Gortmaker | 7095ab3 | 2015-10-17 16:40:31 -0400 | [diff] [blame] | 468 | #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN) |
Paul Gortmaker | aa7b3f3 | 2015-10-17 16:40:28 -0400 | [diff] [blame] | 469 | #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128k(one sector) for env */ |
Jean-Christophe PLAGNIOL-VILLARD | 7e1cda6 | 2008-09-10 22:48:06 +0200 | [diff] [blame] | 470 | #define CONFIG_ENV_SIZE 0x2000 |
Joe Hamman | 1bab0b0 | 2007-08-09 15:11:03 -0500 | [diff] [blame] | 471 | |
| 472 | #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 473 | #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ |
Joe Hamman | 1bab0b0 | 2007-08-09 15:11:03 -0500 | [diff] [blame] | 474 | |
Joe Hershberger | 5a9d7f1 | 2015-06-22 16:15:30 -0500 | [diff] [blame] | 475 | #define CONFIG_CMD_PING |
| 476 | #define CONFIG_CMD_I2C |
| 477 | #define CONFIG_CMD_REGINFO |
Joe Hamman | 1bab0b0 | 2007-08-09 15:11:03 -0500 | [diff] [blame] | 478 | |
| 479 | #if defined(CONFIG_PCI) |
| 480 | #define CONFIG_CMD_PCI |
| 481 | #endif |
| 482 | |
| 483 | #undef CONFIG_WATCHDOG /* watchdog disabled */ |
| 484 | |
| 485 | /* |
| 486 | * Miscellaneous configurable options |
| 487 | */ |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 488 | #define CONFIG_SYS_LONGHELP /* undef to save memory */ |
| 489 | #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ |
Paul Gortmaker | f71e21a | 2015-10-17 16:40:26 -0400 | [diff] [blame] | 490 | #define CONFIG_CMDLINE_EDITING 1 /* add command line history */ |
Joe Hamman | 1bab0b0 | 2007-08-09 15:11:03 -0500 | [diff] [blame] | 491 | |
Jon Loeliger | 5615ef2 | 2007-08-15 11:55:35 -0500 | [diff] [blame] | 492 | #if defined(CONFIG_CMD_KGDB) |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 493 | #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ |
Joe Hamman | 1bab0b0 | 2007-08-09 15:11:03 -0500 | [diff] [blame] | 494 | #else |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 495 | #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ |
Joe Hamman | 1bab0b0 | 2007-08-09 15:11:03 -0500 | [diff] [blame] | 496 | #endif |
| 497 | |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 498 | #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ |
| 499 | #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ |
| 500 | #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ |
Joe Hamman | 1bab0b0 | 2007-08-09 15:11:03 -0500 | [diff] [blame] | 501 | |
| 502 | /* |
| 503 | * For booting Linux, the board info and command line data |
| 504 | * have to be in the first 8 MB of memory, since this is |
| 505 | * the maximum mapped by the Linux kernel during initialization. |
| 506 | */ |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 507 | #define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux*/ |
Joe Hamman | 1bab0b0 | 2007-08-09 15:11:03 -0500 | [diff] [blame] | 508 | |
| 509 | /* Cache Configuration */ |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 510 | #define CONFIG_SYS_DCACHE_SIZE 32768 |
| 511 | #define CONFIG_SYS_CACHELINE_SIZE 32 |
Jon Loeliger | 5615ef2 | 2007-08-15 11:55:35 -0500 | [diff] [blame] | 512 | #if defined(CONFIG_CMD_KGDB) |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 513 | #define CONFIG_SYS_CACHELINE_SHIFT 5 /*log base 2 of the above value*/ |
Joe Hamman | 1bab0b0 | 2007-08-09 15:11:03 -0500 | [diff] [blame] | 514 | #endif |
| 515 | |
Jon Loeliger | 5615ef2 | 2007-08-15 11:55:35 -0500 | [diff] [blame] | 516 | #if defined(CONFIG_CMD_KGDB) |
Joe Hamman | 1bab0b0 | 2007-08-09 15:11:03 -0500 | [diff] [blame] | 517 | #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ |
Joe Hamman | 1bab0b0 | 2007-08-09 15:11:03 -0500 | [diff] [blame] | 518 | #endif |
| 519 | |
| 520 | /* |
| 521 | * Environment Configuration |
| 522 | */ |
| 523 | |
Andy Fleming | 458c389 | 2007-08-16 16:35:02 -0500 | [diff] [blame] | 524 | #define CONFIG_HAS_ETH0 1 |
Joe Hamman | 1bab0b0 | 2007-08-09 15:11:03 -0500 | [diff] [blame] | 525 | #define CONFIG_HAS_ETH1 1 |
| 526 | #define CONFIG_HAS_ETH2 1 |
| 527 | #define CONFIG_HAS_ETH3 1 |
| 528 | |
| 529 | #define CONFIG_IPADDR 192.168.0.50 |
| 530 | |
| 531 | #define CONFIG_HOSTNAME sbc8641d |
Joe Hershberger | 257ff78 | 2011-10-13 13:03:47 +0000 | [diff] [blame] | 532 | #define CONFIG_ROOTPATH "/opt/eldk/ppc_74xx" |
Joe Hershberger | e4da248 | 2011-10-13 13:03:48 +0000 | [diff] [blame] | 533 | #define CONFIG_BOOTFILE "uImage" |
Joe Hamman | 1bab0b0 | 2007-08-09 15:11:03 -0500 | [diff] [blame] | 534 | |
| 535 | #define CONFIG_SERVERIP 192.168.0.2 |
| 536 | #define CONFIG_GATEWAYIP 192.168.0.1 |
| 537 | #define CONFIG_NETMASK 255.255.255.0 |
| 538 | |
| 539 | /* default location for tftp and bootm */ |
| 540 | #define CONFIG_LOADADDR 1000000 |
| 541 | |
| 542 | #define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */ |
| 543 | #undef CONFIG_BOOTARGS /* the boot command will set bootargs */ |
| 544 | |
| 545 | #define CONFIG_BAUDRATE 115200 |
| 546 | |
| 547 | #define CONFIG_EXTRA_ENV_SETTINGS \ |
| 548 | "netdev=eth0\0" \ |
| 549 | "consoledev=ttyS0\0" \ |
| 550 | "ramdiskaddr=2000000\0" \ |
| 551 | "ramdiskfile=uRamdisk\0" \ |
| 552 | "dtbaddr=400000\0" \ |
| 553 | "dtbfile=sbc8641d.dtb\0" \ |
| 554 | "en-wd=mw.b f8100010 0x08; echo -expect:- 08; md.b f8100010 1\0" \ |
| 555 | "dis-wd=mw.b f8100010 0x00; echo -expect:- 00; md.b f8100010 1\0" \ |
| 556 | "maxcpus=1" |
| 557 | |
| 558 | #define CONFIG_NFSBOOTCOMMAND \ |
| 559 | "setenv bootargs root=/dev/nfs rw " \ |
| 560 | "nfsroot=$serverip:$rootpath " \ |
| 561 | "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ |
| 562 | "console=$consoledev,$baudrate $othbootargs;" \ |
| 563 | "tftp $loadaddr $bootfile;" \ |
| 564 | "tftp $dtbaddr $dtbfile;" \ |
| 565 | "bootm $loadaddr - $dtbaddr" |
| 566 | |
| 567 | #define CONFIG_RAMBOOTCOMMAND \ |
| 568 | "setenv bootargs root=/dev/ram rw " \ |
| 569 | "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ |
| 570 | "console=$consoledev,$baudrate $othbootargs;" \ |
| 571 | "tftp $ramdiskaddr $ramdiskfile;" \ |
| 572 | "tftp $loadaddr $bootfile;" \ |
| 573 | "tftp $dtbaddr $dtbfile;" \ |
| 574 | "bootm $loadaddr $ramdiskaddr $dtbaddr" |
| 575 | |
| 576 | #define CONFIG_FLASHBOOTCOMMAND \ |
| 577 | "setenv bootargs root=/dev/ram rw " \ |
| 578 | "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ |
| 579 | "console=$consoledev,$baudrate $othbootargs;" \ |
| 580 | "bootm ffd00000 ffb00000 ffa00000" |
| 581 | |
| 582 | #define CONFIG_BOOTCOMMAND CONFIG_FLASHBOOTCOMMAND |
| 583 | |
| 584 | #endif /* __CONFIG_H */ |